SN74AC74DR ,Dual Positive-Edge-Triggered D-Type Flip-Flops With Clear and Preset/sc/package.Please be aware that an important notice concerning availability, standard warranty, an ..
SN74AC74NSR ,Dual Positive-Edge-Triggered D-Type Flip-Flops With Clear and Preset SCAS521F − AUGUST ..
SN74AC74PW ,Dual Positive-Edge-Triggered D-Type Flip-Flops With Clear and Preset SCAS521F − AUGUST ..
SN74AC74PWR ,Dual Positive-Edge-Triggered D-Type Flip-Flops With Clear and Presetmaximum ratings over operating free-air temperature range (unless otherwise noted)Supply voltage ra ..
SN74AC86 ,Quadruple 2-Input Exclusive-OR Gatesmaximum ratings over operating free-air temperature range (unless otherwise noted)Supply voltage ra ..
SN74AC86D ,Quadruple 2-Input Exclusive-OR Gates SCAS533C − AUGUST 1995 − REVISED OCTOBER 2003 ..
SN74LS195A ,LOW POWER SCHOTTKY
SN74LS195AJ , SHIFT REGISTERS WITH J-/K SERIAL INPUTS
SN74LS195AJ , SHIFT REGISTERS WITH J-/K SERIAL INPUTS
SN74LS195AN ,Universal 4-bit shift registerSN54/74LS195AUNIVERSAL 4-BITSHIFT REGISTERThe SN54/74LS195A is a high speed 4-Bit Shift Register of ..
SN74LS195N ,UNIVERSAL 4-BIT SHIFT REGISTERSN54/74LS195AUNIVERSAL 4-BITSHIFT REGISTERThe SN54/74LS195A is a high speed 4-Bit Shift Register of ..
SN74LS197 ,50/30/100-MHz [RESETTABLE DECADE OR BINARY COUNTERS/LATCHES
SN74AC74-SN74AC74D-SN74AC74DBR-SN74AC74DR-SN74AC74NSR-SN74AC74PW-SN74AC74PWR
Dual Positive-Edge-Triggered D-Type Flip-Flops With Clear and Preset
��������� �������� ���� ����������������������� ������ ���������� ���� ����� ��� ������ SCAS521F − AUGUST 1995 − REVISED OCTOBER 2003 SN54AC74 ...J OR W PACKAGE � 2-V to 6-V V Operation CC SN74AC74 . . . D, DB, N, NS, OR PW PACKAGE � Inputs Accept Voltages to 6 V (TOP VIEW) � Max t of 10 ns at 5 V pd 1CLR 1 14 V CC description/ordering information 1D 2 13 2CLR 1CLK 3 12 2D The ’AC74 devices are dual positive-edge- 1PRE 4 11 2CLK triggered D-type flip-flops. 1Q 5 10 2PRE A low level at the preset (PRE) or clear (CLR) input 6 9 1Q 2Q sets or resets the outputs, regardless of the levels GND 7 8 2Q of the other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting SN54AC74 . . . FK PACKAGE the setup-time requirements is transferred to the (TOP VIEW) outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data 3 2 1 20 19 at D can be changed without affecting the levels 2D 1CLK 4 18 at the outputs. NC NC 5 17 2CLK 1PRE 6 16 NC 15 NC 7 1Q 14 2PRE 8 910111213 NC − No internal connection ORDERING INFORMATION ORDERABLE TOP-SIDE † T PACKAGE A PART NUMBER MARKING PDIP − N Tube SN74AC74N SN74AC74N Tube SN74AC74D SOIC − D SOIC − D AC74 AC74 Tape and reel SN74AC74DR SOP − NS Tape and reel SN74AC74NSR AC74 −40 −40°C to 85 C to 85°C C SSOP − DB Tape and reel SN74AC74DBR AC74 Tube SN74AC74PW TSSOP − PW TSSOP − PW AC74 AC74 Tape and reel SN74AC74PWR CDIP − J Tube SNJ54AC74J SNJ54AC74J CFP − W Tube SNJ54AC74W SNJ54AC74W −55 −55°C to 125 C to 125°C C LCCC − FK Tube SNJ54AC74FK SNJ54AC74FK † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. ���������� ���� �������!��� �" #$��%�! �" �� &$’(�#�!��� )�!%* Copyright 2003, ���)$#!" #������ !� "&%#���#�!���" &%� !+% !%��" �� �%,�" ��"!�$�%�!" �� &��)$#!" #��&(���! !� 0�������12�1�� �(( &����%!%�" ��% !%"!%) "!��)��) -�����!.* ���)$#!��� &��#%""��/ )�%" ��! �%#%""���(. ��#($)% $�(%"" �!+%�-�"% ��!%)* �� �(( �!+%� &��)$#!"� &��)$#!��� !%"!��/ �� �(( &����%!%�"* &��#%""��/ )�%" ��! �%#%""���(. ��#($)% !%"!��/ �� �(( &����%!%�"* 1 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1Q 1D GND 1CLR NC NC V 2Q CC 2Q 2CLR
