SN74AC373DW ,Octal D-Type Transparent Latches With 3-State OutputsSN54AC373, SN74AC373OCTAL D-TYPE TRANSPARENT LATCHESWITH 3-STATE OUTPUTSSCAS540D − OCTOBER 1995 − R ..
SN74AC373DWR ,Octal D-Type Transparent Latches With 3-State Outputsmaximum ratings over operating free-air temperature range (unless otherwise noted)Supply voltage ra ..
SN74AC374DBR ,Octal D-Type Edge-Triggered Flip-Flops with 3-State Outputsmaximum ratings” may cause permanent damage to the device. These are stress ratings only, andfuncti ..
SN74AC374DBR ,Octal D-Type Edge-Triggered Flip-Flops with 3-State OutputsSN54AC374, SN74AC374OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPSWITH 3-STATE OUTPUTSSCAS543E − OCTOBER 19 ..
SN74AC374DW ,Octal D-Type Edge-Triggered Flip-Flops with 3-State OutputsSN54AC374, SN74AC374OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPSWITH 3-STATE OUTPUTSSCAS543E − OCTOBER 19 ..
SN74AC374DWR ,Octal D-Type Edge-Triggered Flip-Flops with 3-State Outputslogic diagram (positive logic)1OE11CLKC121Q31D 1DTo Seven Other Channels†absolute
SN74LS191 ,Synchronous 4-Bit Up/Down Counters With Up/Down Mode Control
SN74LS191DR ,Synchronous 4-Bit Up/Down Counters With Up/Down Mode Control
SN74LS191DR ,Synchronous 4-Bit Up/Down Counters With Up/Down Mode Control
SN74LS191N ,PRESETTABLE BCD/DECADE UP/DOWN COUNTERS PRESETTABLE 4-BIT BINARY UP/DOWN COUNTERSSN54/74LS190SN54/74LS191PRESETTABLE BCD/DECADEUP/DOWN COUNTERSPRESETTABLE 4-BIT BINARYPRESETTABLE B ..
SN74LS191NSR ,Synchronous 4-Bit Up/Down Counters With Up/Down Mode Control
SN74LS192 ,SYNCHRONOUS 4-BIT UP/DOWN COUNTERS (DUAL CLOCK WITH CLEAR)
SN74AC373DW-SN74AC373DWR
Octal D-Type Transparent Latches With 3-State Outputs 20-SOIC -40 to 85
SN54AC373, SN74AC373
OCTAL D-TYPE TRANSPARENT LATCHES
WITH 3-STATE OUTPUTS
SCAS540D − OCTOBER 1995 − REVISED OCTOBER 2003
2-V to 6-V VCC Operation Inputs Accept Voltages to 6 V Max tpd of 9.5 ns at 5 V 3-State Noninverting Outputs Drive Bus
Lines Directly Full Parallel Access for Loading
description/ordering informationThese 8-bit latches feature 3-state outputs
designed specifically for driving highly capacitive
or relatively low-impedance loads. The devices
are particularly suitable for implementing buffer
registers, I/O ports, bidirectional bus drivers, and
working registers.
The eight latches are D-type transparent latches.
When the latch-enable (LE) input is high, the Q
outputs follow the data (D) inputs. When LE is
taken low, the Q outputs are latched at the logic
levels set up at the D inputs.
A buffered output-enable (OE) input can be used
to place the eight outputs in either a normal logic
state (high or low logic levels) or the
high-impedance state. In the high-impedance
state, the outputs neither load nor drive the bus
lines significantly. The high-impedance state and
increased drive provide the capability to drive bus
lines in bus-organized systems without need for
interface or pullup components.
OE does not affect the internal operations of the latches. Old data can be retained or new data can be entered
while the outputs are in the high-impedance state.
ORDERING INFORMATION Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
GND
VCC21 2019
9101112131QOE5D
GND
SN54AC373... FK PACKAGE
(TOP VIEW)
SN54AC373 ...J OR W PACKAGE
SN74AC373... DB, DW, N, NS, OR PW PACKAGE
(TOP VIEW)
