SN74ABT273NSR ,Octal Edge-Triggered D-Type Flip-Flops With Clearmaximum ratings over operating free-air temperature range (unless otherwise noted)Supply voltage ra ..
SN74ABT273PW ,Octal Edge-Triggered D-Type Flip-Flops With Clearlogic diagram (positive logic)1D 2D 3D 4D 5D 6D 7D 8D3 4 7 8 13 14 17 1811CLKCLK(I)1D 1D 1D 1D 1D 1 ..
SN74ABT273PWR ,Octal Edge-Triggered D-Type Flip-Flops With Clear SN54ABT273, SN74ABT273 OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPSWITH CLEARSCBS185B – FEBRUARY 1991 – ..
SN74ABT373DBLE ,Octal Transparent D-Type Latches With 3-State Outputsmaximum ratings over operating free-air temperature range (unless otherwise noted)Supply voltage ra ..
SN74ABT373DBR ,Octal Transparent D-Type Latches With 3-State Outputs SN54ABT373, SN74ABT373 OCTAL TRANSPARENT D-TYPE LATCHESWITH 3-STATE OUTPUTSSCBS155D – JANUARY 1991 ..
SN74ABT373DW ,Octal Transparent D-Type Latches With 3-State Outputslogic diagram (positive logic)1OE11LEC121Q31D1DTo Seven Other Channels‡absolute
SN74LS14 ,Hex schmitt-trigger invertersFeatures... 18.4 Device Functional Modes.... 132 Applications..... 19 Application and Implementatio ..
SN74LS145DR ,BCD-To-Decimal Decoders/Drivers
SN74LS145DR ,BCD-To-Decimal Decoders/Drivers
SN74LS147N ,10-LINE-TO-4-LINE AND 8-LINE-TO-3-LINE PRIORITY ENCODERS
SN74LS148DR2 ,10-Line-to-4-Line and 8-Line-to-3-Line Priority Encodersorder data line is encoded. Both devices have data inputs and outputswhich are active at the low lo ..
SN74LS148J ,8-line to 3-line priority encoder ..
SN74ABT273-SN74ABT273DBR-SN74ABT273DBRG4-SN74ABT273DW-SN74ABT273DWR-SN74ABT273NSR-SN74ABT273PW-SN74ABT273PWR
Octal Edge-Triggered D-Type Flip-Flops With Clear
at VCC = 5 V, TA = 25°C High-Drive Outputs (–32-mA IOH, 64-mA IOL) Package Options Include Plastic
Small-Outline (DW), Shrink Small-Outline
(DB), and Thin Shrink Small-Outline (PW)
Packages, Ceramic Chip Carriers (FK),
Plastic (N) and Ceramic (J) DIPs, and
Ceramic Flat (W) Package
descriptionThe ’ABT273 are 8-bit positive-edge-triggered
D-type flip-flops with a direct clear (CLR) input.
They are particularly suitable for implementing
buffer and storage registers, shift registers, and
pattern generators.
Information at the data (D) inputs meeting the
setup time requirements is transferred to the
Q outputs on the positive-going edge of the clock
pulse. Clock triggering occurs at a particular
voltage level and is not directly related to the
transition time of the positive-going pulse. When
the clock (CLK) input is at either the high or low
level, the D input signal has no effect at the output.
The SN54ABT273 is characterized for operation over the full military temperature range of –55°C to 125°C. The
SN74ABT273 is characterized for operation from –40°C to 85°C.
FUNCTION TABLE
(each flip-flop)Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SN54ABT273... FK PACKAGE
(TOP VIEW)1QCLR5D
GND
CLK
GND
CLK
