SN74ABT18640DL ,Scan Test Devices With 18-Bit Inverting Bus TransceiversSN54ABT18640, SN74ABT18640 SCAN TEST DEVICESWITH 18-BIT INVERTING BUS TRANSCEIVERSSCBS267C – FEBRUA ..
SN74ABT18646 ,Scan Test Devices With 18-Bit Bus Transceivers And Registers SN74ABT18646 SCAN TEST DEVICEWITH 18-BIT TRANSCEIVER AND REGISTERSCBS131A – AUGUST 1992 – REVISED ..
SN74ABT2240A ,Octal Buffers And Line/MOS Drivers With 3-State Outputsmaximum ratings” may cause permanent damage to the device. These are stress ratings only, andfuncti ..
SN74ABT2240ADB , OCTAL BUFFERS AND LINE/MOS DRIVERS WITH 3-STATE OUTPUTS
SN74ABT2240ADW ,Octal Buffers And Line/MOS Drivers With 3-State Outputs SN54ABT2240A, SN74ABT2240A OCTAL BUFFERS AND LINE/MOS DRIVERSWITH 3-STATE OUTPUTSSCBS232E – JANUAR ..
SN74ABT2240ADWR ,Octal Buffers And Line/MOS Drivers With 3-State Outputslogic diagram (positive logic)1 191OE 2OE218 11 91A1 1Y1 2A1 2Y1416 13 71A2 1Y2 2A2 2Y2614 15 51Y3 ..
SN74LS125ADBR ,Quadruple Bus Buffers With 3-State Outputslogic diagram (each gate)’125, ’LS125AGAY’126, ’LS126AGAYY = A2POST OFFICE BOX 655303 • DALLAS, TEX ..
SN74LS125ADBR ,Quadruple Bus Buffers With 3-State Outputsmaximum ratings over operating free-air temperature (unless otherwise noted)(’125 and ’126) Supply ..
SN74LS125ADR ,Quadruple Bus Buffers With 3-State OutputsSN54125, SN54126, SN54LS125A, SN54LS126A, SN74125, SN74126, SN74LS125A, SN74LS126AThe SN54125, SN54 ..
SN74LS125AML1 ,Quad 3-State Buffers
SN74LS125AML1 ,Quad 3-State Buffers
SN74LS125AMR1 ,Quad 3-State Buffers
SN74ABT18640DL
Scan Test Devices With 18-Bit Inverting Bus Transceivers
1149.1-1990 (JTAG) Test Access Port and
Boundary-Scan Architecture SCOPE Instruction Set
– IEEE Standard 1149.1-1990 Required
Instructions and Optional CLAMP and
HIGHZ
– Parallel-Signature Analysis at Inputs
– Pseudo-Random Pattern Generation
From Outputs
– Sample Inputs/Toggle Outputs
– Binary Count From Outputs
– Device Identification
– Even-Parity Opcodes State-of-the-Art EPIC-II B BiCMOS Design
Significantly Reduces Power Dissipation Packaged in Plastic Shrink Small-Outline
(DL) and Thin Shrink Small-Outline (DGG)
Packages and 380-mil Fine-Pitch Ceramic
Flat (WD) Packages
descriptionThe ’ABT18640 scan test devices with 18-bit
inverting bus transceivers are members of the
Texas Instruments SCOPE testability
integrated-circuit family. This family of devices
supports IEEE Standard 1149.1-1990 boundary
scan to facilitate testing of complex circuit-board
assemblies. Scan access to the test circuitry is
accomplished via the 4-wire test access port
(TAP) interface.
In the normal mode, these devices are 18-bit inverting bus transceivers. They can be used either as two 9-bit
transceivers or one 18-bit transceiver. The test circuitry can be activated by the TAP to take snapshot samples
of the data appearing at the device pins or to perform a self test on the boundary-test cells. Activating the TAP
in the normal mode does not affect the functional operation of the SCOPE bus transceivers.
Data flow is controlled by the direction-control (DIR) and output-enable (OE) inputs. Data transmission is
allowed from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at DIR. OE can
be used to disable the device so that the buses are effectively isolated.
In the test mode, the normal operation of the SCOPE bus transceivers is inhibited and the test circuitry is
enabled to observe and control the I/O boundary of the device. When enabled, the test circuitry can perform
boundary-scan test operations according to the protocol described in IEEE Standard 1149.1-1990.
1B1
1B2
GND
1B3
1B4CC
1B5
1B6
1B7
GND
1B8
1B9
2B1
2B2
2B3
2B4
GND
2B5
2B6
2B7
VCC
2B8
2B9
GND
2DIR
TDO
TMS
1A1
1A2
GND
1A3
1A4CC
1A5
1A6
1A7
GND
1A8
1A9
2A1
2A2
2A3
2A4
GND
2A5
2A6
2A7
VCC
2A8
2A9
GND
2OE
TDI
TCK
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
