SN74ABT16841DLR ,20-Bit Bus-Interface D-Type Latches With 3-State Outputs SN54ABT16841, SN74ABT16841 20-BIT BUS-INTERFACE D-TYPE LATCHESWITH 3-STATE OUTPUTSSCBS222C – SEPTE ..
SN74ABT16843DLR ,18-Bit Bus-Interface D-Type Latches With 3-State Outputs SN54ABT16843, SN74ABT16843 18-BIT BUS-INTERFACE D-TYPE LATCHESWITH 3-STATE OUTPUTSSCBS223E – OCTOB ..
SN74ABT16863DL ,18-Bit Bus Transceivers With 3-State Outputs SN54ABT16863, SN74ABT16863 18-BIT BUS TRANSCEIVERSWITH 3-STATE OUTPUTSSCBS225C – JUNE 1992 – REVIS ..
SN74ABT16952 ,16-Bit Registered Transceivers With 3-State Outputs SN54ABT16952, SN74ABT16952 16-BIT REGISTERED TRANSCEIVERSWITH 3-STATE OUTPUTSSCBS082C – FEBRUARY 1 ..
SN74ABT16952DGGR ,16-Bit Registered Transceivers With 3-State Outputs SN54ABT16952, SN74ABT16952 16-BIT REGISTERED TRANSCEIVERSWITH 3-STATE OUTPUTSSCBS082C – FEBRUARY 1 ..
SN74ABT16952DGGR ,16-Bit Registered Transceivers With 3-State Outputs SN54ABT16952, SN74ABT16952 16-BIT REGISTERED TRANSCEIVERSWITH 3-STATE OUTPUTSSCBS082C – FEBRUARY 1 ..
SN74LS125A ,LOW POWER SCHOTTKYmaximum ratings” may cause permanent damage to the device. These are stress ratings only, andfuncti ..
SN74LS125AD ,Quad 3-state buffermaximum ratings” may cause permanent damage to the device. These are stress ratings only, andfuncti ..
SN74LS125ADBR ,Quadruple Bus Buffers With 3-State Outputslogic diagram (each gate)’125, ’LS125AGAY’126, ’LS126AGAYY = A2POST OFFICE BOX 655303 • DALLAS, TEX ..
SN74LS125ADBR ,Quadruple Bus Buffers With 3-State Outputsmaximum ratings over operating free-air temperature (unless otherwise noted)(’125 and ’126) Supply ..
SN74LS125ADR ,Quadruple Bus Buffers With 3-State OutputsSN54125, SN54126, SN54LS125A, SN54LS126A, SN74125, SN74126, SN74LS125A, SN74LS126AThe SN54125, SN54 ..
SN74LS125AML1 ,Quad 3-State Buffers
SN74ABT16841DLR
20-Bit Bus-Interface D-Type Latches With 3-State Outputs
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0) Latch-Up Performance Exceeds 500 mA Per
JEDEC Standard JESD-17 Typical VOLP (Output Ground Bounce)
< 0.8 V at VCC = 5 V, TA = 25°C High-Impedance State During Power Up
and Power Down Distributed VCC and GND Pin Configuration
Minimizes High-Speed Switching Noise Flow-Through Architecture Optimizes PCB
Layout High-Drive Outputs (–32-mA IOH , 64-mA IOL) Package Options Include Plastic 300-mil
Shrink Small-Outline (DL) Package and
380-mil Fine-Pitch Ceramic Flat (WD)
Package Using 25-mil Center-to-Center
Spacings
descriptionThese 20-bit latches feature 3-state outputs
designed specifically for driving highly capacitive
or relatively low-impedance loads. They are
particularly suitable for implementing buffer
registers, I/O ports, bidirectional bus drivers, and
working registers.
The ’ABT16841 can be used as two 10-bit latches or one 20-bit latch. The 20 transparent D-type latches provide
true data at the outputs. While the latch-enable (1LE or 2LE) input is high, the Q outputs of the corresponding
10-bit latch follow the D inputs. When LE is taken low, the Q outputs are latched at the levels set up at the D
inputs.
A buffered output-enable (1OE or 2OE) input can be used to place the outputs of the corresponding 10-bit latch
in either a normal logic state (high or low logic levels) or a high-impedance state. In the high-impedance state,
the outputs neither load nor drive the bus lines significantly.
The output-enable input does not affect the internal operation of the latches. Old data can be retained or new
data can be entered while the outputs are in the high-impedance state.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
1Q2
GND
1Q3
1Q4CC
1Q5
1Q6
1Q7
GND
1Q8
1Q9
1Q10
2Q1
2Q2
2Q3
GND
2Q4
2Q5
2Q6
VCC
2Q7
2Q8
GND
2Q9
2Q10
2OE
1D2
GND
1D3
1D4CC
1D5
1D6
1D7
GND
1D8
1D9
1D10
2D1
2D2
2D3
GND
2D4
2D5
2D6
VCC
2D7
2D8
GND
2D9
2D10
2LE
