SN74ABT16833DL ,Dual 8-Bit To 9-Bit Parity Bus Transceivers SN54ABT16833, SN74ABT16833 DUAL 8-BIT TO 9-BIT PARITY BUS TRANSCEIVERS SCBS097D – FEBRUARY 1991 – ..
SN74ABT16841DLR ,20-Bit Bus-Interface D-Type Latches With 3-State Outputs SN54ABT16841, SN74ABT16841 20-BIT BUS-INTERFACE D-TYPE LATCHESWITH 3-STATE OUTPUTSSCBS222C – SEPTE ..
SN74ABT16843DLR ,18-Bit Bus-Interface D-Type Latches With 3-State Outputs SN54ABT16843, SN74ABT16843 18-BIT BUS-INTERFACE D-TYPE LATCHESWITH 3-STATE OUTPUTSSCBS223E – OCTOB ..
SN74ABT16863DL ,18-Bit Bus Transceivers With 3-State Outputs SN54ABT16863, SN74ABT16863 18-BIT BUS TRANSCEIVERSWITH 3-STATE OUTPUTSSCBS225C – JUNE 1992 – REVIS ..
SN74ABT16952 ,16-Bit Registered Transceivers With 3-State Outputs SN54ABT16952, SN74ABT16952 16-BIT REGISTERED TRANSCEIVERSWITH 3-STATE OUTPUTSSCBS082C – FEBRUARY 1 ..
SN74ABT16952DGGR ,16-Bit Registered Transceivers With 3-State Outputs SN54ABT16952, SN74ABT16952 16-BIT REGISTERED TRANSCEIVERSWITH 3-STATE OUTPUTSSCBS082C – FEBRUARY 1 ..
SN74LS125A ,LOW POWER SCHOTTKYmaximum ratings” may cause permanent damage to the device. These are stress ratings only, andfuncti ..
SN74LS125AD ,Quad 3-state buffermaximum ratings” may cause permanent damage to the device. These are stress ratings only, andfuncti ..
SN74LS125ADBR ,Quadruple Bus Buffers With 3-State Outputslogic diagram (each gate)’125, ’LS125AGAY’126, ’LS126AGAYY = A2POST OFFICE BOX 655303 • DALLAS, TEX ..
SN74LS125ADBR ,Quadruple Bus Buffers With 3-State Outputsmaximum ratings over operating free-air temperature (unless otherwise noted)(’125 and ’126) Supply ..
SN74LS125ADR ,Quadruple Bus Buffers With 3-State OutputsSN54125, SN54126, SN54LS125A, SN54LS126A, SN74125, SN74126, SN74LS125A, SN74LS126AThe SN54125, SN54 ..
SN74LS125AML1 ,Quad 3-State Buffers
SN74ABT16833DL
Dual 8-Bit To 9-Bit Parity Bus Transceivers
Per JEDEC Standard JESD-17 Typical VOLP (Output Ground Bounce)
< 1 V at VCC = 5 V, TA = 25°C Distributed VCC and GND Pin Configuration
Minimizes High-Speed Switching Noise Flow-Through Architecture Optimizes
PCB Layout High-Drive Outputs (–32-mA IOH, 64-mA IOL) Parity-Error Flag With Parity
Generator/Checker Register for Storage of Parity-Error Flag Package Options Include Plastic 300-mil
Shrink Small-Outline (DL) and Thin Shrink
Small-Outline (DGG) Packages and 380-mil
Fine-Pitch Ceramic Flat (WD) Package
Using 25-mil Center-to-Center Spacings
descriptionThe ’ABT16833 consist of two noninverting 8-bit
to 9-bit parity bus transceivers and are designed
for communication between data buses. For each
transceiver, when data is transmitted from the
A bus to the B bus, an odd-parity bit is generated
and output on the parity I/O pin (1PARITY or
2PARITY). When data is transmitted from the
B bus to the A bus, 1PARITY (or 2PARITY) is
configured as an input and combined with the
B-input data to generate an active-low error flag if
odd parity is not detected.
The error (1ERR or 2ERR) output is configured as an open-collector output. The B-to-A parity-error flag is
clocked into 1ERR (or 2ERR) on the low-to-high transition of the clock (1CLK or 2CLK) input. 1ERR (or 2ERR)
is cleared (set high) by taking the clear (1CLR or 2CLR) input low.
The output-enable (OEA and OEB) inputs can be used to disable the device so that the buses are effectively
isolated. When both OEA and OEB are low, data is transferred from the A bus to the B bus and inverted parity
is generated. Inverted parity is a forced error condition that gives the designer more system diagnostic
capability.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
1ERR
GND
1A1
1A2
VCC
1A3
1A4
1A5
GND
1A6
1A7
1A8
2A1
2A2
2A3
GND
2A4
2A5
2A6CC
2A7
2A8
GND
2ERR
2CLK
2OEB
1PARITY
GND
1B1
1B2
VCC
1B3
1B4
1B5
GND
1B6
1B7
1B8
2B1
2B2
2B3
GND
2B4
2B5
2B6CC
2B7
2B8
GND
2PARITY
2CLR
2OEA
