SN74ABT16827DLR ,20-Bit Buffers/Drivers With 3-State Outputslogic diagram (positive logic)1 281OE1 2OE156 291OE2 2OE255 2 42 151A1 1Y1 2A1 2Y1To Nine Other Cha ..
SN74ABT16827DLR ,20-Bit Buffers/Drivers With 3-State Outputs SN54ABT16827, SN74ABT16827 20-BIT BUFFERS/DRIVERSWITH 3-STATE OUTPUTSSCBS220C – JUNE 1992 – REVISE ..
SN74ABT16833DL ,Dual 8-Bit To 9-Bit Parity Bus Transceivers SN54ABT16833, SN74ABT16833 DUAL 8-BIT TO 9-BIT PARITY BUS TRANSCEIVERS SCBS097D – FEBRUARY 1991 – ..
SN74ABT16841DLR ,20-Bit Bus-Interface D-Type Latches With 3-State Outputs SN54ABT16841, SN74ABT16841 20-BIT BUS-INTERFACE D-TYPE LATCHESWITH 3-STATE OUTPUTSSCBS222C – SEPTE ..
SN74ABT16843DLR ,18-Bit Bus-Interface D-Type Latches With 3-State Outputs SN54ABT16843, SN74ABT16843 18-BIT BUS-INTERFACE D-TYPE LATCHESWITH 3-STATE OUTPUTSSCBS223E – OCTOB ..
SN74ABT16863DL ,18-Bit Bus Transceivers With 3-State Outputs SN54ABT16863, SN74ABT16863 18-BIT BUS TRANSCEIVERSWITH 3-STATE OUTPUTSSCBS225C – JUNE 1992 – REVIS ..
SN74LS123N ,RETRIGGERABLE MONOSTABLE MULTIVIBRATORStiming resistor that allows the circuits to be used with only an externalcapacitor. Once triggered, ..
SN74LS125A ,LOW POWER SCHOTTKYmaximum ratings” may cause permanent damage to the device. These are stress ratings only, andfuncti ..
SN74LS125AD ,Quad 3-state buffermaximum ratings” may cause permanent damage to the device. These are stress ratings only, andfuncti ..
SN74LS125ADBR ,Quadruple Bus Buffers With 3-State Outputslogic diagram (each gate)’125, ’LS125AGAY’126, ’LS126AGAYY = A2POST OFFICE BOX 655303 • DALLAS, TEX ..
SN74LS125ADBR ,Quadruple Bus Buffers With 3-State Outputsmaximum ratings over operating free-air temperature (unless otherwise noted)(’125 and ’126) Supply ..
SN74LS125ADR ,Quadruple Bus Buffers With 3-State OutputsSN54125, SN54126, SN54LS125A, SN54LS126A, SN74125, SN74126, SN74LS125A, SN74LS126AThe SN54125, SN54 ..
SN74ABT16827-SN74ABT16827DL-SN74ABT16827DLR
20-Bit Buffers/Drivers With 3-State Outputs
JEDEC Standard JESD-17 Typical VOLP (Output Ground Bounce) < 1 V
at VCC = 5 V, TA = 25°C High-Impedance State During Power Up
and Power Down Distributed VCC and GND Pin Configuration
Minimizes High-Speed Switching Noise Flow-Through Architecture Optimizes PCB
Layout High-Drive Outputs (–32-mA IOH , 64-mA IOL) Package Options Include Plastic 300-mil
Shrink Small-Outline (DL) Package and
380-mil Fine-Pitch Ceramic Flat (WD)
Package Using 25-mil Center-to-Center
Spacings
descriptionThe ’ABT16827 are noninverting 20-bit buffers
composed of two 10-bit sections with separate
output-enable signals. For either 10-bit buffer
section, the two output-enable (1OE1 and 1OE2
or 2OE1 and 2OE2) inputs must both be low for
the corresponding Y outputs to be active. If either
output-enable input is high, the outputs of that
10-bit buffer section are in the high-impedance
state.
When VCC is between 0 and 2.1 V, the device is in the high-impedance state during power up or power down.
However, to ensure the high-impedance state above 2.1 V, OE should be tied to VCC through a pullup resistor;
the minimum value of the resistor is determined by the current-sinking capability of the driver.
The SN54ABT16827 is characterized for operation over the full military temperature range of –55°C to 125°C.
The SN74ABT16827 is characterized for operation from –40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
1Y2
GND
1Y3
1Y4CC
1Y5
1Y6
1Y7
GND
1Y8
1Y9
1Y10
2Y1
2Y2
2Y3
GND
2Y4
2Y5
2Y6
VCC
2Y7
2Y8
GND
2Y9
2Y10
2OE1
1A2
GND
1A3
1A4CC
1A5
1A6
1A7
GND
1A8
1A9
1A10
2A1
2A2
2A3
GND
2A4
2A5
2A6
VCC
2A7
2A8
GND
2A9
2A10
2OE2
