SN74ABT16601DLR ,18-Bit Universal Bus Transceivers With 3-State Outputslogic diagram (positive logic)1OEAB56CLKENAB55CLKAB2LEAB28LEBA30CLKBA29CLKENBA27OEBACE3A11D 54B1C1C ..
SN74ABT16623DL ,16-Bit Bus Transceivers With 3-State Outputs SN54ABT16623, SN74ABT16623 16-BIT BUS TRANSCEIVERSWITH 3-STATE OUTPUTSSCBS211B – FEBRUARY 1991 – R ..
SN74ABT16623DLR ,16-Bit Bus Transceivers With 3-State Outputsmaximum ratings” may cause permanent damage to the device. These are stress ratings only, andfuncti ..
SN74ABT16640DLR ,16-Bit Bus Transceivers With 3-State Outputs SN54ABT16640, SN74ABT16640 16-BIT BUS TRANSCEIVERSWITH 3-STATE OUTPUTSSCBS107C – APRIL 1992 – REVI ..
SN74ABT16646 ,16-Bit Bus Transceivers And Registers With 3-State Outputs
SN74ABT16646DL ,16-Bit Bus Transceivers And Registers With 3-State Outputs
SN74LS122DR ,Retriggerable monostable multivibrator
SN74LS122DR2 ,Retriggerable Monostable Multivibrators2SN74LS122 SN74LS123LS122 FUNCTIONAL TABLE LS123 FUNCTIONAL TABLEINPUTS OUTPUTS INPUTS OUTPUTSCLEAR ..
SN74LS122DR2 ,Retriggerable Monostable Multivibratorstiming resistor that allows the circuits to be used with only an externalcapacitor. Once triggered, ..
SN74LS122N ,RETRIGGERABLE MONOSTABLE MULTIVIBRATORStiming resistor that allows the circuits to be used with only an externalcapacitor. Once triggered, ..
SN74LS122NSR ,Retriggerable monostable multivibrator
SN74LS122NSR ,Retriggerable monostable multivibrator
SN74ABT16601-SN74ABT16601DGGR-SN74ABT16601DL-SN74ABT16601DLR
18-Bit Universal Bus Transceivers With 3-State Outputs
Combines D-Type Latches and D-Type
Flip-Flops for Operation in Transparent,
Latched, Clocked, or Clock-Enabled Mode Latch-Up Performance Exceeds 500 mA Per
JEDEC Standard JESD-17 Typical VOLP (Output Ground Bounce)
< 0.8 V at VCC = 5 V, TA = 25°C Flow-Through Architecture Optimizes PCB
Layout Package Options Include Plastic 300-mil
Shrink Small-Outline (DL) and Thin Shrink
Small-Outline (DGG) Packages and 380-mil
Fine-Pitch Ceramic Flat (WD) Package
Using 25-mil Center-to-Center Spacings
descriptionThese 18-bit universal bus transceivers combine
D-type latches and D-type flip-flops to allow data
flow in transparent, latched, clocked, and
clock-enabled modes.
Data flow in each direction is controlled by
output-enable (OEAB and OEBA), latch-enable
(LEAB and LEBA), and clock (CLKAB and
CLKBA) inputs. The clock can be controlled by the
clock-enable (CLKENAB and CLKENBA) inputs.
For A-to-B data flow, the device operates in the
transparent mode when LEAB is high. When
LEAB is low, the A data is latched if CLKAB is held
at a high or low logic level. If LEAB is low, the
A data is stored in the latch/flip-flop on the
low-to-high transition of CLKAB. Output enable
OEAB is active low. When OEAB is low, the
outputs are active. When OEAB is high, the
outputs are in the high-impedance state.
Data flow for B to A is similar to that of A to B, but uses OEBA, LEBA, CLKBA, and CLKENBA.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
The SN54ABT16601 is characterized for operation over the full military temperature range of –55°C to 125°C.
The SN74ABT16601 is characterized for operation from –40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
GND
VCC
GND
A10
A11
A12
GND
A13
A14
A15
VCC
A16
A17
GND
A18
OEBA
LEBA
GND
VCC
GND
B10
B11
B12
GND
B13
B14
B15
VCC
B16
B17
GND
B18
CLKBA
CLKENBA
