SN74ABT16501DGGR ,18-Bit Universal Bus Transceivers With 3-State Outputslogic diagram (positive logic)1OEAB55CLKAB2LEAB28LEBA30CLKBA27OEBA3A1 1D 54B1C1CLK1DC1CLKTo 17 Othe ..
SN74ABT16501DL ,18-Bit Universal Bus Transceivers With 3-State Outputs SN54ABT16501, SN74ABT16501 18-BIT UNIVERSAL BUS TRANSCEIVERSWITH 3-STATE OUTPUTSSCBS086C – FEBRUAR ..
SN74ABT16501DL ,18-Bit Universal Bus Transceivers With 3-State Outputsmaximum ratings over operating free-air temperature range (unless otherwise noted)Supply voltage ra ..
SN74ABT16501DLR ,18-Bit Universal Bus Transceivers With 3-State Outputsmaximum ratings over operating free-air temperature range (unless otherwise noted)Supply voltage ra ..
SN74ABT16540ADL ,16-Bit Buffers/Drivers With 3-State Outputs SN54ABT16540, SN74ABT16540A 16-BIT BUFFERS/DRIVERSWITH 3-STATE OUTPUTSSCBS208C – FEBRUARY 1991 – R ..
SN74ABT16540ADLR ,16-Bit Buffers/Drivers With 3-State Outputsmaximum ratings over operating free-air temperature range (unless otherwise noted)Supply voltage ra ..
SN74LS112AN ,Dual JK negative edge-triggered flip-flopSN54/74LS112ADUAL JK NEGATIVEEDGE-TRIGGERED FLIP-FLOPThe SN54/74LS112A dual JK flip-flop
SN74LS112ANSR ,Dual J-K Negative-Edge-Triggered Flip-Flops With Clear And Preset
SN74LS112N ,DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOPSN54/74LS112ADUAL JK NEGATIVEEDGE-TRIGGERED FLIP-FLOPThe SN54/74LS112A dual JK flip-flop
SN74LS114AN ,Dual JK negative edge-triggered flip-flop
SN74LS122DR ,Retriggerable monostable multivibrator
SN74LS122DR2 ,Retriggerable Monostable Multivibrators2SN74LS122 SN74LS123LS122 FUNCTIONAL TABLE LS123 FUNCTIONAL TABLEINPUTS OUTPUTS INPUTS OUTPUTSCLEAR ..
SN74ABT16501-SN74ABT16501DGGR-SN74ABT16501DL-SN74ABT16501DLR
18-Bit Universal Bus Transceivers With 3-State Outputs
Combines D-Type Latches and D-Type
Flip-Flops for Operation in Transparent,
Latched, or Clocked Mode ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0) Latch-Up Performance Exceeds 500 mA Per
JEDEC Standard JESD-17 Typical VOLP (Output Ground Bounce)
< 0.8 V at VCC = 5 V, TA = 25°C Flow-Through Architecture Optimizes PCB
Layout Package Options Include Plastic 300-mil
Shrink Small-Outline (DL) and Thin Shrink
Small-Outline (DGG) Packages and 380-mil
Fine-Pitch Ceramic Flat (WD) Package
Using 25-mil Center-to-Center Spacings
descriptionThese 18-bit universal bus transceivers consist of
storage elements that can operate either as
D-type latches or D-type flip-flops to allow data
flow in transparent or clocked modes.
Data flow in each direction is controlled by
output-enable (OEAB and OEBA), latch-enable
(LEAB and LEBA), and clock (CLKAB and
CLKBA) inputs. For A-to-B data flow, the device
operates in the transparent mode when LEAB is
high. When LEAB is low, the A data is latched if
CLKAB is held at a high or low logic level. If LEAB
is low, the A data is stored in the latch/flip-flop on
the low-to-high transition of CLKAB. When OEAB
is high, the outputs are active. When OEAB is low,
the outputs are in the high-impedance state.
Data flow for B to A is similar to that of A to B but uses OEBA, LEBA, and CLKBA. The output enables are
complementary (OEAB is active high and OEBA is active low).
To ensure the high-impedance state during power up or power down, OE should be tied to GND through a
pulldown resistor and OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is
determined by the current-sourcing/current-sinking capability of the driver.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
GNDCC
GND
A10
A11
A12
GND
A13
A14
A15
VCC
A16
A17
GND
A18
OEBA
LEBA
GNDCC
GND
B10
B11
B12
GND
B13
B14
B15
VCC
B16
B17
GND
B18
CLKBA
GND
