SN74ABT16373ADL ,16-Bit Transparent D-Type Latches With 3-State Outputsmaximum ratings” may cause permanent damage to the device. These are stress ratings only, andfuncti ..
SN74ABT16373ADLR ,16-Bit Transparent D-Type Latches With 3-State Outputsmaximum ratings” may cause permanent damage to the device. These are stress ratings only, andfuncti ..
SN74ABT16374 ,16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS
SN74ABT16374A ,16-Bit Edge-Triggered D-Type Fflip-Flops With 3-State Outputslogic diagram (positive logic)1 241OE 2OE48 252CLK1CLKC1C1 2 132Q11Q147 361D2D11D1 1DTo Seven Other ..
SN74ABT16374ADGGR ,16-Bit Edge-Triggered D-Type Fflip-Flops With 3-State Outputsmaximum ratings over operating free-air temperature range (unless otherwise noted)Supply voltage ra ..
SN74ABT16374ADL ,16-Bit Edge-Triggered D-Type Fflip-Flops With 3-State Outputslogic diagram (positive logic)1 241OE 2OE48 252CLK1CLKC1C1 2 132Q11Q147 361D2D11D1 1DTo Seven Other ..
SN74LS10D ,TRIPLE 3-INPUT NAND GATE
SN74LS10D ,TRIPLE 3-INPUT NAND GATE
SN74LS11 ,Triple 3-input positive-AND gates
SN74LS11 ,Triple 3-input positive-AND gates
SN74LS112 , DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH PRESET AND CLEAR
SN74LS112ADR ,Dual J-K Negative-Edge-Triggered Flip-Flops With Clear And Preset
SN74ABT16373A-SN74ABT16373ADGGR-SN74ABT16373ADL-SN74ABT16373ADLR
16-BIT TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS
JEDEC Standard JESD-17 Typical V OLP (Output Ground Bounce)
< 0.8 V at VCC = 5 V, TA = 25°C High-Impedance State During Power Up
and Power Down Distributed VCC and GND Pin Configuration
Minimizes High-Speed Switching Noise Flow-Through Architecture Optimizes PCB
Layout High-Drive Outputs (–32-mA IOH, 64-mA IOL) Package Options Include Plastic 300-mil
Shrink Small-Outline (DL) and Thin Shrink
Small-Outline (DGG) Packages and 380-mil
Fine-Pitch Ceramic Flat (WD) Package
Using 25-mil Center-to-Center Spacings
descriptionThe ’ABT16373A are 16-bit transparent D-type
latches with 3-state outputs designed specifically
for driving highly capacitive or relatively
low-impedance loads. They are particularly
suitable for implementing buffer registers, I/O
ports, bidirectional bus drivers, and working
registers.
These devices can be used as two 8-bit latches or one 16-bit latch. When the latch-enable (LE) input is high,
the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the levels set up
at the D inputs.
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high
or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive
the bus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus
lines without need for interface or pullup components.
OE does not affect internal operations of the latch. Old data can be retained or new data can be entered while
the outputs are in the high-impedance state.
When VCC is between 0 and 2.1 V, the device is in the high-impedance state during power up or power down.
However, to ensure the high-impedance state above 2.1 V, OE should be tied to VCC through a pullup resistor;
the minimum value of the resistor is determined by the current-sinking capability of the driver.
The SN54ABT16373A is characterized for operation over the full military temperature range of –55°C to 125°C.
The SN74ABT16373A is characterized for operation from –40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
1Q2
GND
1Q3
1Q4CC
1Q5
1Q6
GND
1Q7
1Q8
2Q1
2Q2
GND
2Q3
2Q4
VCC
2Q5
2Q6
GND
2Q7
2Q8
2OE
1D2
GND
1D3
1D4CC
1D5
1D6
GND
1D7
1D8
2D1
2D2
GND
2D3
2D4
VCC
2D5
2D6
GND
2D7
2D8
2LE
