SN74ABT162841DL ,20-Bit Bus-Interface D-Type Latches With 3-State Outputs/sc/package.Please be aware that an important notice concerning availability, standard warranty, an ..
SN74ABT16373 ,16-Bit Transparent D-Type Latches With 3-State Outputs 48-SSOP -40 to 85
SN74ABT16373 ,16-Bit Transparent D-Type Latches With 3-State Outputs 48-SSOP -40 to 85
SN74ABT16373A ,16-Bit Transparent D-Type Latches With 3-State Outputsmaximum ratings over operating free-air temperature range (unless otherwise noted)Supply voltage ra ..
SN74ABT16373ADGGR ,16-Bit Transparent D-Type Latches With 3-State Outputsmaximum ratings over operating free-air temperature range (unless otherwise noted)Supply voltage ra ..
SN74ABT16373ADGGR ,16-Bit Transparent D-Type Latches With 3-State Outputs SN54ABT16373A, SN74ABT16373A 16-BIT TRANSPARENT D-TYPE LATCHESWITH 3-STATE OUTPUTSSCBS160C – DECEM ..
SN74LS109ANSR ,Dual J-K Positive-Edge-Triggered Flip-Flops With Clear And Preset
SN74LS109ANSR ,Dual J-K Positive-Edge-Triggered Flip-Flops With Clear And Preset
SN74LS10D ,TRIPLE 3-INPUT NAND GATE
SN74LS10D ,TRIPLE 3-INPUT NAND GATE
SN74LS11 ,Triple 3-input positive-AND gates
SN74LS11 ,Triple 3-input positive-AND gates
SN74ABT162841DL
20-Bit Bus-Interface D-Type Latches With 3-State Outputs
Typical V OLP (Output Ground Bounce)<0.8 V at VCC = 5 V, TA = 25°C High-Impedance State During Power Up
and Power Down Ioff and Power-Up 3-State Support Hot
Insertion Distributed VCC and GND Pins Minimize
High-Speed Switching Noise Flow-Through Architecture Optimizes PCB
Layout Latch-Up Performance Exceeds 500 mA Per
JEDEC Standard JESD-17
description/ordering informationThese 20-bit transparent D-type latches feature
noninverting 3-state outputs designed specifically
for driving highly capacitive or relatively
low-impedance loads. They are particularly
suitable for implementing buffer registers, I/O
ports, bidirectional bus drivers, and working
registers.
The ’ABT162841 devices can be used as two
10-bit latches or one 20-bit latch. While the
latch-enable (1LE or 2LE) input is high, the Q
outputs of the corresponding 10-bit latch follow
the data (D) inputs. When LE is taken low, the
Q outputs are latched at the levels set up at the D
inputs.
ORDERING INFORMATION†Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
1Q2
GND
1Q3
1Q4
VCC
1Q5
1Q6
1Q7
GND
1Q8
1Q9
1Q10
2Q1
2Q2
2Q3
GND
2Q4
2Q5
2Q6CC
2Q7
2Q8
GND
2Q9
2Q10
2OE
1D2
GND
1D3
1D4
VCC
1D5
1D6
1D7
GND
1D8
1D9
1D10
2D1
2D2
2D3
GND
2D4
2D5
2D6CC
2D7
2D8
GND
2D9
2D10
2LE
