SN74ABT125DR ,Quadruple Bus Buffer Gates With 3-State Outputsmaximum ratings” may cause permanent damage to the device. These are stress ratings only, andfuncti ..
SN74ABT125DRG4 ,Quadruple Bus Buffer Gates With 3-State Outputs 14-SOIC -40 to 85maximum ratings” may cause permanent damage to the device. These are stress ratings only, andfuncti ..
SN74ABT125DRG4 ,Quadruple Bus Buffer Gates With 3-State Outputs 14-SOIC -40 to 85/sc/package.Please be aware that an important notice concerning availability, standard warranty, an ..
SN74ABT125N ,Quadruple Bus Buffer Gates With 3-State Outputsmaximum ratings” may cause permanent damage to the device. These are stress ratings only, andfuncti ..
SN74ABT125NSR ,Quadruple Bus Buffer Gates With 3-State OutputsSN54ABT125, SN74ABT125QUADRUPLE BUS BUFFER GATESWITH 3-STATE OUTPUTSSCBS182I − FEBRUARY 1997 − REVI ..
SN74ABT125PW ,Quadruple Bus Buffer Gates With 3-State Outputsmaximum ratings over operating free-air temperature range (unless otherwise noted)Supply voltage ra ..
SN74LS06D ,Hex inverter buffers / drivers with high-voltage outputsElectrical Characteristics....... 512.3 Receiving Notification of Documentation Updates 126.6 Switc ..
SN74LS06DBR ,Hex inverter buffers / drivers with high-voltage outputsFeatures... 19 Application and Implementation........ 92 Applications..... 19.1 Application Informa ..
SN74LS06DR ,Hex inverter buffers / drivers with high-voltage outputsMaximum Ratings(1)over operating free-air temperature range (unless otherwise noted)MIN MAX UNITSup ..
SN74LS06N ,Hex inverter buffers / drivers with high-voltage outputsMaximum Ratings.. 411.2 Layout Examples...... 116.2 ESD Ratings ...... 412 Device and Documentation ..
SN74LS06NE4 ,Hex inverter buffers / drivers with high-voltage outputs 14-PDIP 0 to 70Logic Diagram (Positive Logic)1 21A 1Y3 42A 2Y5 63A 3Y9 84A 4Y11 105A 5Y13 126A 6YPin numbers shown ..
SN74LS06NSR ,Hex inverter buffers / drivers with high-voltage outputsFeatures... 19 Application and Implementation........ 92 Applications..... 19.1 Application Informa ..
SN74ABT125-SN74ABT125D-SN74ABT125DBLE-SN74ABT125DBR-SN74ABT125DR-SN74ABT125DRG4-SN74ABT125N-SN74ABT125NSR-SN74ABT125PW-SN74ABT125PWR-SN74ABT125RGYR
Quadruple Bus Buffer Gates With 3-State Outputs
SN54ABT125, SN74ABT125
QUADRUPLE BUS BUFFER GATES
WITH 3-STATE OUTPUTS
SCBS182I − FEBRUARY 1997 − REVISED NOVEMBER 2002
Typical VOLP (Output Ground Bounce)
<1 V at VCC = 5 V, TA = 25°C High-Drive Outputs (−32-mA IOH, 64-mA IOL) Ioff and Power-Up 3-State Support Hot
Insertion Latch-Up Performance Exceeds 500 mA Per
JEDEC Standard JESD-17 ESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
SN54ABT125 ...J OR W PACKAGE
SN74ABT125... D, DB, N, NS,
OR PW PACKAGE
(TOP VIEW)1OE
2OE
GND
VCC
4OE
3OE1 2019
3OE
2OE1OENC3A4OE
GND
SN54ABT125... FK PACKAGE
(TOP VIEW)NC − No internal connection
SN74ABT125... RGY PACKAGE
(TOP VIEW)4OE
3OE
2OE
1OE
GND
description/ordering informationThe ’ABT125 quadruple bus buffer gates feature independent line drivers with 3-state outputs. Each output is
disabled when the associated output-enable (OE) input is high.
These devices are fully specified for hot-insertion applications using Ioff and power-up 3-state. The Ioff circuitry
disables the outputs, preventing damaging current backflow through the devices when they are powered down.
The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down,
which prevents driver conflict.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
ORDERING INFORMATION Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
