SN65LVDS96DGGR ,Serdes (Serializer/Deserializer) ReceiverBLOCK DIAGRAMSerial-In/Parallel-OutShift RegisterA0PD0Serial In A,B, ...GD1A0MCLK D2D3D4D5D6Serial- ..
SN65LVDS96DGGRG4 ,Serdes (Serializer/Deserializer) Receiver 48-TSSOP -40 to 85SLLS296H–MAY 1998–REVISED JULY 2006CLKINPrevious Cycle Current Cycle Next CycleA0D6 D5 D4 D3 D2 D1 ..
SN65LVDT100D ,2Gbps LVDS/LVPECL/CML to LVDS Repeater/Translator
SN65LVDT100DGKR ,2Gbps LVDS/LVPECL/CML to LVDS Repeater/Translator
SN65LVDT100DGKRG4 ,2Gbps LVDS/LVPECL/CML to LVDS Repeater/Translator 8-VSSOP -40 to 85
SN65LVDT100DRG4 , DIFFERENTIAL TRANSLATOR/REPEATER
SN74HCT139D ,Dual 2-Line To 4-Line Decoders/Demultiplexersmaximum ratings” may cause permanent damage to the device. These are stress ratings only, andfuncti ..
SN74HCT139DR ,Dual 2-Line To 4-Line Decoders/Demultiplexersmaximum ratings over operating free-air temperature range (unless otherwise noted)Supply voltage ra ..
SN74HCT139DR ,Dual 2-Line To 4-Line Decoders/Demultiplexers SCLS066D − MARCH 1982 − REVISED SEPTEM ..
SN74HCT139N ,Dual 2-Line To 4-Line Decoders/Demultiplexers/sc/package.Please be aware that an important notice concerning availability, standard warranty, an ..
SN74HCT14 ,Hex Schmitt-Trigger InvertersSample & Support &Product Tools &TechnicalCommunityBuyFolder Documents SoftwareSN54HCT14,SN74HCT14S ..
SN74HCT14D ,Hex Schmitt-Trigger InvertersMaximum Ratings.. 411.1 Layout Guidelines.... 106.2 ESD Ratings........ 411.2 Layout Example....... ..
SN65LVDS96-SN65LVDS96DGG-SN65LVDS96DGGR-SN65LVDS96DGGRG4
Serdes (Serializer/Deserializer) Receiver
www.ti.com
FEATURESD17
D18
D19
D20
LVDSGND
A0M
A0P
A1M
A1P
LVDSVCC
LVDSGND
A2M
A2P
LVDSGND
PLLGND
PLLGND
CLKOUT
VCC
D16
D15
D14
GND
D13
VCC
D12
D11
D10
GND
VCC
GND
VCC
GND
DGG PACKAGE
(TOP VIEW)
DESCRIPTION
SLLS296H–MAY 1998–REVISED JULY 2006
LVDS SERDES RECEIVER 3:21 Data Channel Compressionat upto
1.428 Gigabits/s Throughput Suited for Point-to-Point Subsystem
Communication With Very EMI 3 Data Channels and Clock
Differential Channelsin and21 Data and
Clock Low-Voltage TTL Channels Out Operates Froma Single 3.3-V Supply and 250 (Typ) 5-V Tolerant SHTDN Input Rising Clock Edge Triggered Outputs Bus Pins Tolerate 4-kV HBM ESD Packagedin Thin Shrink
Package With20 Mil Terminal Pitch Consumes <1 mW When Wide Phase-Lock Input Frequency Range MHzto68 MHz No External Components for PLL Inputs Meetor Exceed theof
ANSI EIA/TIA-644 Standard Industrial Temperature Qualified= –40°Cto 85°C Replacement for the DS90CR216The SN65LVDS96 LVDS serdes (serializer/deserializer) receiver contains serial-in 7-bit parallel-out shift
registers,a 7× clock synthesizer, and four low-voltage differential signaling (LVDS) line receiversina single
integrated circuit. These functions allow receiptof synchronous data from compatible transmitter, such asthe
SN65LVDS95, over four balanced-pair conductors and expansionto21 bits single-ended LVTTL synchronous
dataata lower transfer rate.
When receiving, the high-speed datais received and loaded into registersat the rateof seven times the
LVDS input clock (CLKIN). Theis then unloadedtoa 21-bit wide LVTTL parallel busat the CLKIN rate.A
phase-locked loop clock synthesizer circuit generatesa7× clock for internal andan output clock for the presents valid dataon the rising edgeof output clock (CLKOUT). line termination resistors for the differential inputs and littleor no control.
