SN65LVDS93DGGR ,Serdes (Serializer/Deserializer) Transmitter........ SLLS302G–MAY 1998–REVISED MAY 2009ÉÉÉÉÉÉÉÉÉÉÉÉÉÉD0ÉÉÉÉÉÉÉÉÉÉÉÉÉÉCLKINorÉÉÇÇÇÉÉÇÇCLKINÉÉÇÇÇ ..
SN65LVDS93DGGRG4 ,Serdes (Serializer/Deserializer) Transmitter 56-TSSOP -40 to 85These devices have limited built-in ESD protection. The leads should be shorted together or the dev ..
SN65LVDS94 ,Serdes (Serializer/Deserializer) ReceiverSLLS298F–MAY 1998–REVISED JANUARY 2006These devices have limited built-in ESD protection. The leads ..
SN65LVDS94DGG ,Serdes (Serializer/Deserializer) ReceiverMAXIMUM RATINGS(1)over operating free-air temperature (unless otherwise noted)UNIT(2)V Supply volta ..
SN65LVDS94DGGG4 ,Serdes (Serializer/Deserializer) Receiver 56-TSSOP SLLS298F–MAY 1998–REVISED JANUARY 2006CLKINPrevious Cycle Current Cycle Next CycleA0D7 D6 D4 D3 D2 ..
SN65LVDS94DGGR ,Serdes (Serializer/Deserializer) ReceiverSLLS298F–MAY 1998–REVISED JANUARY 2006LVDS SERDES RECEIVER
SN74HCT08D ,Quadruple 2-Input Positive-AND Gatesmaximum ratings” may cause permanent damage to the device. These are stress ratings only, andfuncti ..
SN74HCT08DBLE ,Quadruple 2-Input Positive-AND GatesSN54HCT08, SN74HCT08QUADRUPLE 2-INPUT POSITIVE-AND GATESSCLS063D – NOVEMBER 1988 – REVISED AUIGUST ..
SN74HCT08DBR ,Quadruple 2-Input Positive-AND Gateslogic diagram (positive logic)AYB†absolute
SN74HCT08DR ,Quadruple 2-Input Positive-AND GatesSN54HCT08, SN74HCT08QUADRUPLE 2-INPUT POSITIVE-AND GATESSCLS063D – NOVEMBER 1988 – REVISED AUIGUST ..
SN74HCT08N ,Quadruple 2-Input Positive-AND Gatesmaximum ratings” may cause permanent damage to the device. These are stress ratings only, andfuncti ..
SN74HCT08NSR ,Quadruple 2-Input Positive-AND Gatesmaximum ratings over operating free-air temperature range (unless otherwise noted)Supply voltage ra ..
SN65LVDS93DGG-SN65LVDS93DGGR-SN65LVDS93DGGRG4
Serdes (Serializer/Deserializer) Transmitter
1FEATURES
DESCRIPTIONVCC
GND
D10
VCC
D11
D12
D13
GND
D14
D15
D16
CLKSEL
D17
D18
D19
GND
D20
D21
D22
D23
VCC
D24
D25
GND
D27
LVDSGND
Y1M
Y1P
Y2M
Y2P
LVDSVCC
LVDSGND
Y3M
Y3P
CLKOUTM
CLKOUTP
Y4M
Y4P
LVDSGND
PLLGND
PLLVCC
PLLGND
SHTDN
CLKIN
D26
GND
DGG PACKAGE
(TOP VIEW)
SN65LVDS93
www.ti.com................................................................................................................................................................. SLLS302G–MAY 1998–REVISED MAY 2009
LVDS SERDES TRANSMITTERWhen transmitting, data bits D0 through D27 are
each loaded into registers upon the edgeof the input•
28:4 Data Channel Compressionat upto clock signal (CLKIN). The risingor falling edgeof the
1.904 Gigabits per Second Throughput clock can selected via the clock select (CLKSEL)•
Suited for Point-to-Point Subsystem pin. Theof CLKINis multiplied seven times
Communication With Low EMI and thento serially unload the data registersin
7-bit slices. The four serial streams and a•
28 Data Channels Plus Clockin Low-Voltage phase-locked clock (CLKOUT) are then output to
TTL and4 Data Channels Plus Clock Out LVDS output drivers. The frequencyof CLKOUTis
Low-Voltage Differential the same the input clock, CLKIN.•
Selectable Risingor Clock Edge
Triggered Inputs Bus Pins Tolerate 6-kV HBM ESD Operates Froma Single 3.3-V Supply and
250 mW (Typ) 5-V Tolerant Data Inputs Packagedin Thin Shrink Small-Outline
Package With20 Mil Pitch Consumes<1 mW When Disabled Wide Phase-Lock Input Frequency Range MHzto68 MHz No External Components Required for PLL Outputs Meetor Exceed the Requirementsof
ANSI EIA/TIA-644 Standard Industrial Temperature QualifiedTA= –40°C 85°C Replacement for theThe SN65LVDS93 serdes (serializer/
deserializer) transmitter four 7-bit parallel-
load serial-out shift registers,a 7נclock synthesizer,
and five low-voltage differential signaling (LVDS)
driversina single integrated circuit. These functions
allow 28 bits of single-ended LVTTL data to be
synchronously transmitted over five balanced-pair
conductors for receiptby compatible receiver, such the SN65LVDS94.
