SN65LVDS84AQDGG ,Flatlink Transmittermaximum ratings” may cause permanent damage to the device. These are stress ratings only, andfuncti ..
SN65LVDS84AQDGGR ,Flatlink Transmitter SN75LVDS84A, SN65LVDS84AQ FLATLINK TRANSMITTER SLLS354E – MAY 1999 – REVISED JANUARY 2001DGG PAC ..
SN65LVDS84AQDGGRQ1 ,Automotive Catalog FlatLink Transmitter 48-TSSOP -40 to 125FEATURESDGG PACKAGE2• 21:3 Data Channel Compression at up to(TOP VIEW)196 Mbytes/s ThroughputD4 D3• ..
SN65LVDS86AQDGGRG4 ,Automotive Catalog FlatLink Receiver 48-TSSOP -40 to 125FEATURESDGG PACKAGE2• 3:21 Data Channel Expansion at up to(TOP VIEW)178.5 Mbytes/s ThroughputD17 V• ..
SN65LVDS86AQDGGRQ1 ,Automotive Catalog FlatLink Receiver 48-TSSOP -40 to 125 SLLS768A–AUGUST 2006–REVISED JANUARY 2012ÇÇÉÉÇÇÇÉÉÇÇÇÇÉÉÇÇÇÉÉÇÇCLKINÇÇÉÉÇÇÇÉÉÇÇPrevious Cycle Curr ..
SN65LVDS93ADGGR ,10MHzFeatures 2 Applications1• Industrial Temperature Range –40°C to 85°C • LCD Display Panel Drivers• L ..
SN74HCT08D ,Quadruple 2-Input Positive-AND Gatesmaximum ratings” may cause permanent damage to the device. These are stress ratings only, andfuncti ..
SN74HCT08DBLE ,Quadruple 2-Input Positive-AND GatesSN54HCT08, SN74HCT08QUADRUPLE 2-INPUT POSITIVE-AND GATESSCLS063D – NOVEMBER 1988 – REVISED AUIGUST ..
SN74HCT08DBR ,Quadruple 2-Input Positive-AND Gateslogic diagram (positive logic)AYB†absolute
SN74HCT08DR ,Quadruple 2-Input Positive-AND GatesSN54HCT08, SN74HCT08QUADRUPLE 2-INPUT POSITIVE-AND GATESSCLS063D – NOVEMBER 1988 – REVISED AUIGUST ..
SN74HCT08N ,Quadruple 2-Input Positive-AND Gatesmaximum ratings” may cause permanent damage to the device. These are stress ratings only, andfuncti ..
SN74HCT08NSR ,Quadruple 2-Input Positive-AND Gatesmaximum ratings over operating free-air temperature range (unless otherwise noted)Supply voltage ra ..
SN65LVDS84AQDGG-SN65LVDS84AQDGGR
Flatlink Transmitter
21 Data Channels Plus Clock InLow-Voltage TTL Inputs and 3 Data
Channels Plus Clock Out Low-Voltage
Differential Signaling (LVDS) Outputs Operates From a Single 3.3-V Supply and
89 mW (Typ) Ultralow-Power 3.3-V CMOS Version of the
SN75LVDS84. Power Consumption About
One Third of the ’LVDS84 Packaged in Thin Shrink Small-Outline
Package (TSSOP) With 20 Mil Terminal
Pitch Consumes Less Than 0.54 mW When
Disabled Wide Phase-Lock Input Frequency Range:
31 MHz to 75 MHz No External Components Required for PLL Outputs Meet or Exceed the Requirements
of ANSI EIA/TIA-644 Standard SSC Tracking Capability of 3% Center
Spread at 50-kHz Modulation Frequency Improved Replacement for SN75LVDS84
and NSC’s DS90CF363A 3-V Device Available in Q-Temp Automotive
High Reliability Automotive Applications
Configuration Control / Print Support
Qualification to Automotive Standards
descriptionThe SN75LVDS84A and SN65LVDS84AQ FlatLink transmitters contains three 7-bit parallel-load serial-out shift
registers, and four low-voltage differential signaling (LVDS) line drivers in a single integrated circuit. These
functions allow 21 bits of single-ended LVTTL data to be synchronously transmitted over 3 balanced-pair
conductors for receipt by a compatible receiver, such as the SN75LVDS82 or SN75LVDS86/86A.
When transmitting, data bits D0 – D20 are each loaded into registers of the ’LVDS84A upon the falling edge.
The internal PLL is frequency-locked to CLKIN and then used to unload the data registers in 7-bit slices. The
three serial streams and a phase-locked clock (CLKOUT) are then output to LVDS output drivers. The frequency
of CLKOUT is the same as the input clock, CLKIN.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
GNDCC
D10
GND
D11
D12
D13
D14
GND
D15
D16
D17CC
D18
D19
GND
LVDSGND
Y0M
Y0P
Y1M
Y1P
LVDSVCC
LVDSGND
Y2M
Y2P
CLKOUTM
CLKOUTP
LVDSGND
PLLGND
PLLVCC
PLLGND
SHTDN
CLKIN
D20
NC – Not Connected
