SN65LVDS33DRG4 ,Quad LVDS Receiver with -4 to 5V Common-mode Range 16-SOIC -40 to 85logic diagram (positive logic)On LVDT Products(TOP VIEW)• TSSOP Packaging (33 Only)G1B 1 16 V• Comp ..
SN65LVDS33PW ,Quad LVDS Receiver with -4 to 5V Common-mode Range.(2) Add the suffix R for taped and reeled carrier.DESCRIPTION (CONTINUED)The receivers can withsta ..
SN65LVDS33PWR ,Quad LVDS Receiver with -4 to 5V Common-mode RangeThese devices have limited built-in ESD protection. The leads should be shorted together or the dev ..
SN65LVDS33PWRG4 ,Quad LVDS Receiver with -4 to 5V Common-mode Range 16-TSSOP -40 to 85logic diagram (positive logic)industry. These receivers provide an input voltagerange specification ..
SN65LVDS3486 ,Quad LVDS Receiverelectrical characteristics• Operate With a Single 3.3-V Supplyof low-voltage differential signaling ..
SN65LVDS3486BD ,Quad LVDS Receiver with -2 to 4.4V Common-mode RangeLogic Diagram (TOP VIEW)(positive logic)portfolio and is not necessarily a replacement forolder LVD ..
SN74HCT02PWR ,Quadruple 2-Input Positive-NOR GatesSN54HCT02, SN74HCT02QUADRUPLE 2-INPUT POSITIVE-NOR GATESSCLS065E – NOVEMBER 1988 – REVISED JULY 200 ..
SN74HCT04 ,Hex Invertersmaximum ratings over operating free-air temperature range (unless otherwise noted)Supply voltage ra ..
SN74HCT04D ,Hex Invertersmaximum ratings” may cause permanent damage to the device. These are stress ratings only, andfuncti ..
SN74HCT04DR ,Hex Inverterslogic diagram (positive logic)AY†absolute
SN74HCT04DRG4 ,Hex Inverters 14-SOIC -40 to 85 SN54HCT04, SN74HCT04 HEX INVERTERS SCLS042D – JULY 1986 – REVISED JULY 2003* Operating Voltage Ran ..
SN74HCT04N ,Hex Invertersmaximum ratings over operating free-air temperature range (unless otherwise noted)Supply voltage ra ..
SN65LVDS33D-SN65LVDS33DRG4-SN65LVDS33PW-SN65LVDS33PWR-SN65LVDS33PWRG4
Quad LVDS Receiver with -4 to 5V Common-mode Range
SN65LVDS33, SN65LVDT33 SN65LVDS34, SN65LVDT34 www.ti.com SLLS490B –MARCH 2001–REVISED NOVEMBER 2004 HIGH-SPEED DIFFERENTIAL RECEIVERS Check for Samples: SN65LVDS33, SN65LVDT33, SN65LVDS34, SN65LVDT34 1 The high-speed switching of LVDS signals usually FEATURES (1) necessitates the use of a line impedance matching • 400-Mbps Signaling Rate and 200-Mxfr/s resistor at the receiving-end of the cable or Data Transfer Rate transmission media. The SN65LVDT series of • Operates With a Single 3.3-V Supply receivers eliminates this external resistor by integrating it with the receiver. The nonterminated • -4 V to 5 V Common-Mode Input Voltage SN65LVDS series is also available for multidrop or Range other termination circuits. • Differential Input Thresholds <±50 mV With 50 mV of Hysteresis Over Entire Common-Mode SN65LVDS33D, SN65LVDT33D Input Voltage Range SN65LVDS33PW, SN65LVDT33PW • Integrated 110-Ω Line Termination Resistors D OR PW PACKAGE logic diagram (positive logic) On LVDT Products (TOP VIEW) • TSSOP Packaging (33 Only) G 1B 1 16 V • Complies With TIA/EIA-644 (LVDS) CC G 1A 2 15 4B SN65LVDT33 ONLY • Active Failsafe Assures a High-Level Output 1Y 4A 3 14 1A With No Input 1Y G 4 13 4Y • Bus-Pin ESD Protection Exceeds 15 kV HBM 1B 2Y 5 12 G • Input Remains High-Impedance on Power 2A 6 11 3Y 2A Down 2B 7 10 3A 2Y • TTL Inputs Are 5 V Tolerant 2B GND 8 9 3B • Pin-Compatible With the AM26LS32, 3A SN65LVDS32B,µA9637, SN65LVDS9637B 3Y 3B (1) The signalling rate of a line, is the number of voltage transitions that are made per second expressed in the units 4A bps (bits per second). 4Y 4B DESCRIPTION SN65LVDS34D, SN65LVDT34D This family of four LVDS data line receivers offers the widest common-mode input voltage range in the D PACKAGE (TOP VIEW) logic diagram (positive logic) industry. These receivers provide an input voltage range specification compatible with a 5-V PECL V 1 8 1A signal as well as an overall increased ground-noise CC 1A 1Y 2 7 1B tolerance. They are in industry standard footprints 1Y with integrated termination as an option. 2Y 3 6 2A 1B SN65LVDT34 ONLY GND 4 5 2B Precise control of the differential input voltage 2A thresholds allows for inclusion of 50 mV of input 2Y voltage hysteresis to improve noise rejection on 2B slowly changing input signals. The input thresholds are still no more than ±50 mV over the full input common-mode voltage range. 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Copyright © 2001–2004, Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
