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SN74HC74QPWRG4Q1 ,Automotive Catalog Dual D-Type Positive-Edge-Triggered Flip-Flops With Clear and Preset 14-TSSOP -40 to 125SN74HC74-Q1DUAL D-TYPE POSITIVE-EDGE-TRIGGERED FLIP-FLOPWITH CLEAR AND PRESETSCLS577A − MARCH 2004 ..
SN65LVDS151-SN65LVDS151DA
MuxIt (TM) Serializer-Transmitter
www.ti.com
FEATURESVCC
GND
LCRI+
LCRI–
CI_EN
DI–9
DI–8
DI–7
DI–6
DI–5
DI–4
DI–3
DI–2
DI–1
DI–0
GND
CI–
CI+
LVI
MCI–
MCI+
GND
VCC
LCO+
LCO–
VCC
LCO_EN
VCC5
GND
DO+
DO–
SN65LVDS151DA
(Marked as 65LVDS151)
DESCRIPTION
SN65LVDS151
SLLS444A–DECEMBER 2000
MuxIt™ SERIALIZER-TRANSMITTER A Memberof MuxIt™
Serializer-Deserializer Building-Block Chip
Family Supports Serializationof upto 10 Bitsof
Parallel Dataat Rates upto 200 Mbps PLL Lock/Valid Providedto Enable Link
Data Transfers Cascadable With Additional SN65LVDS151
MuxIt Serializer-Transmitters for Wider
Parallel Input Channel Widths LVDS Compatible Differential Inputs and
Outputs Meet Exceed the Requirementsof
ANSI TIA/EIA-644-A LVDS Inputs Outputs ESD Protection
Exceeds12 kV LVTTL Compatible Inputs for Lock/Valid,
Enables, and Data Inputs Are 5-V
Tolerant Operates WithV Supply Packagedin DA Thin Shrink
Small-Outline With26 Mil Terminal
PitchMuxItisa familyof multiple-chip building blocks for implementing parallel data serializers and
deserializers. The allows for wide parallel datato be transmitted througha reduced numberof
transmission lines distances greater than can be achieved witha single-ended (e.g., LVTTLor LVCMOS)
data interface. Theof bits multiplexed per transmission lineis user-selectable and allows for higher
transmission efficiencies than with existing fixed ratio solutions. MuxIt utilizes the LVDS (TIA/EIA-644-A) low
voltage differential technologyfor communications between the data source and data destination.
The MuxIt family includes three devices supporting simplex communications: the SN65LVDS150 phase
locked loop frequency multiplier, the SN65LVDS151 serializer-transmitter, and the SN65LVDS152
receiver-deserializer.
The SN65LVDS151ofa 10-bit parallel-in/serial-out shift register, three LVDS differential transmission receivers,a pair LVDS differential transmission line drivers, plus associated input buffers.It accepts uptoof user data parallel data inputs (DI-0→ DI-9) and serializes (multiplexes) the data for transmission transmission line link. Twoor more SN65LVDS151 units may be connectedin series (cascaded) data paths for higher serialization values. Datais transmitted over the LVDSatM times parallel data clock frequency. The multiplexing ratioM,or numberof bits per data
