SN65LVDS150PW ,MuxIt (TM) PLL Frequency MultiplierFEATURESSN65LVDS150 • A Member of the MuxIt™ Serializer-PW PACKAGE(Marked as 65LVDS150)Deserializer ..
SN65LVDS150PWG4 ,MuxIt (TM) PLL Frequency Multiplier 28-TSSOP -40 to 85SLLS443–DECEMBER 2000(1)Frequency Multiplier Value TableRECOMMENDED fINMULTIPLIER(MHz)M1 M2 M3 M4 M ..
SN65LVDS151 ,MuxIt (TM) Serializer-TransmitterSLLS444A–DECEMBER 2000These devices have limited built-in ESD protection. The leads should be short ..
SN65LVDS151DA ,MuxIt (TM) Serializer-TransmitterFEATURESSN65LVDS151DA• A Member of the MuxIt™(Marked as 65LVDS151)Serializer-Deserializer Building- ..
SN65LVDS152 ,MuxIt (TM) Receiver-DeserializerFEATURESSN65LVDS152DA2• A Member of the MuxIt™ Serializer-(Marked as 65LVDS152)Deserializer Buildin ..
SN65LVDS179D ,Single Full-Duplex LVDS TransceiverBlock Diagram. 173 Description....... 110.3 Feature Description.. 174 Revision History........ 210. ..
SN74HC74N ,Dual D-Type Positive-Edge-Triggered Flip-Flops With Clear and PresetMaximum Ratings.. 411.1 Layout Guidelines.... 136.2 ESD Ratings ...... 411.2 Layout Example....... ..
SN74HC74NSR ,Dual D-Type Positive-Edge-Triggered Flip-Flops With Clear and PresetMaximum Ratings.. 411.1 Layout Guidelines.... 136.2 ESD Ratings ...... 411.2 Layout Example....... ..
SN74HC74PW ,Dual D-Type Positive-Edge-Triggered Flip-Flops With Clear and PresetSample & Support &Product Tools &TechnicalCommunityBuyFolder Documents SoftwareSN54HC74,SN74HC74SCL ..
SN74HC74PWR ,Dual D-Type Positive-Edge-Triggered Flip-Flops With Clear and PresetSample & Support &Product Tools &TechnicalCommunityBuyFolder Documents SoftwareSN54HC74,SN74HC74SCL ..
SN74HC74PWRG4 ,Dual D-Type Positive-Edge-Triggered Flip-Flops With Clear and Preset 14-TSSOP -40 to 85Sample & Support &Product Tools &TechnicalCommunityBuyFolder Documents SoftwareSN54HC74,SN74HC74SCL ..
SN74HC74QPWRG4Q1 ,Automotive Catalog Dual D-Type Positive-Edge-Triggered Flip-Flops With Clear and Preset 14-TSSOP -40 to 125SN74HC74-Q1DUAL D-TYPE POSITIVE-EDGE-TRIGGERED FLIP-FLOPWITH CLEAR AND PRESETSCLS577A − MARCH 2004 ..
SN65LVDS150-SN65LVDS150PW-SN65LVDS150PWG4
MuxIt (TM) PLL Frequency Multiplier
www.ti.com
FEATURESVCC
CRI+
CRI–
GND
BSEL
GND
LCRO–
LCRO+
VCC
GND
GND
MCO+
MCO–
GND
LCRO_EN
LVO
SN65LVDS150
PW PACKAGE
(Marked as 65LVDS150)NC – No internal connection
DESCRIPTION
SLLS443–DECEMBER 2000
MuxIt™ PLL FREQUENCY A Memberof the Serializer-
Deserializer Building-Block Chip Family Pin Selectable Multiplier Ratios
Between4 and Input Clock Frequencies From5to50 MHz Multiplied Clock upto
400 MHz Internal Loop Filters and Low PLL-Jitterofps RMS Typicalat 200 MHz LVDS Compatible Differential Inputs and
Outputs Meetor the Requirementsof
ANSI EIA/TIA-644-A LVTTL Compatible Inputs Are5V Tolerant LVDS Inputs and ESD Protection
Exceeds12 kV Operates From 3.3V Supply Packagedin 28-Pin Thin Shrink Small-Outline
Package With26 Terminal PitchThe MuxItisa family general-purpose, multiple-chip building for implementing parallel data serializers
and deserializers. The system allows for wide parallel data transmitted througha reduced numberof
differential transmission lines over distances greater than can achieved witha single-ended (e.g., LVTTLor
LVCMOS) data interface. The numberof bits multiplexed per lineis user selectable, allowing for
higher transmission than with other existing ratio solutions. Muxlt utilizes the LVDS
(TIA/EIA-644) low voltage differential signaling technology for communications between the data source and data
destination.
The MuxIt family initially includes three devices supporting simplex communications; The SN65LVDS150 Phase
Locked Loop-Frequency Multiplier, The SN65LVDS151 Serializer-Transmitter, and The SN65LVDS152
Receiver-Deserializer.
The SN65LVDS150a PLL based frequency multiplier designed for use with the other membersof the MuxIt
familyof serializers deserializers. The frequency multiplication ratiois pin selectable overa wide rangeof
values from4 through 40to accommodatea broad spectrum needs. No external filter components are
needed.A PLL lock outputis available which maybe usedto enable link data transfers. designof the SN65LVDS150 allowsitto be usedat either transmit endor the receive endof the MuxIt link. The differential clock reference input (CRI)is driven the system's parallel data clock whenat theof the the link clock whenat the destination endof the link. The differential clock reference be driven an LVDS differential signal,ora single ended clockof either polarity. For
