SN65LVDS105PWR ,1 LVTTL:4 LVDS Clock Fanout BufferBlock Diagram... 152 Applications..... 19.3 Feature Description.... 153 Description....... 19.4 Dev ..
SN65LVDS108DBT ,1:8 LVDS Clock Fanout Bufferelectrical characteristics of low-voltage differential signaling(LVDS). LVDS, as specified in EIA/T ..
SN65LVDS108DBTR ,1:8 LVDS Clock Fanout Buffermaximum ratings may cause permanent damage to the device. These are stress ratingsonly, and functio ..
SN65LVDS108DBTRG4 ,1:8 LVDS Clock Fanout Buffer 38-TSSOP -40 to 85FEATURESDBT PACKAGE• One Line Receiver and Eight Line Drivers(TOP VIEW)Configured as an 8-Port LVDS ..
SN65LVDS109DBT ,Dual 4-Port LVDS RepeaterFEATURESLVDS signaling technique, is for point-to-point or• Two Line Receivers and Eight ('109) orp ..
SN65LVDS109DBTR ,Dual 4-Port LVDS Repeaterelectrical characteristics of low-voltage differential ENH G1Z26 39signaling (LVDS). LVDS, as speci ..
SN74HC74D ,Dual D-Type Positive-Edge-Triggered Flip-Flops With Clear and PresetMaximum Ratings.. 411.1 Layout Guidelines.... 136.2 ESD Ratings ...... 411.2 Layout Example....... ..
SN74HC74DBR ,Dual D-Type Positive-Edge-Triggered Flip-Flops With Clear and PresetElectrical Characteristics....... 512.2 Related Links.. 146.6 Timing Requirements... 612.3 Communit ..
SN74HC74DBR ,Dual D-Type Positive-Edge-Triggered Flip-Flops With Clear and PresetFeatures 3 DescriptionThe SNx4HC74 devices contain two independent D-1• Wide Operating Voltage Rang ..
SN74HC74DR ,Dual D-Type Positive-Edge-Triggered Flip-Flops With Clear and PresetLogic Diagram (Positive Logic)PRECCLKCQC TGCCCCTGD TGTGQCCCCLR1An IMPORTANT NOTICE at the end of th ..
SN74HC74DRG4 ,Dual D-Type Positive-Edge-Triggered Flip-Flops With Clear and Preset 14-SOIC -40 to 85Logic Diagram (Positive Logic)PRECCLKCQC TGCCCCTGD TGTGQCCCCLR1An IMPORTANT NOTICE at the end of th ..
SN74HC74MPWREP ,Enhanced Product Dual D-Type Positive Edge Triggered Flip Flop With Clear And Preset 14-TSSOP -55 to 125FEATURES• Controlled Baseline • Wide Operating Voltage Range of 2 V to 6 V– One Assembly Site • Out ..
SN65LVDS105D-SN65LVDS105DR-SN65LVDS105PW-SN65LVDS105PWG4-SN65LVDS105PWR
1 LVTTL:4 LVDS Clock Fanout Buffer
EN1
EN2Product
Folder
Sample &
Buy
Technical
Documents
Tools &
Software
Support &
Community
SN65LVDS104, SN65LVDS105SLLS396G –SEPTEMBER 1999–REVISED DECEMBER 2015
SN65LVDS10x 4-Port LVDS and 4-Port TTL-to-LVDS Repeaters Features 3 DescriptionThe SN65LVDS10x area differential line receiver and Receiver and Drivers Meetor Exceed the a LVTTL input (respectively) connected to fourRequirementsof ANSI EIA/TIA-644 Standard differential line drivers that implement the electrical– SN65LVDS105 Receives Low-Voltage TTL characteristics of low-voltage differential signaling(LVTTL) Levels (LVDS). LVDS,as specifiedin EIA/TIA-644isa data
signaling technique that offers low-power, low-noise– SN65LVDS104 Receives Differential Input
coupling, and switching speedsto transmit dataatLevels, ±100 mV relatively long distances. (Note: The ultimate rate and• Typical Data Signaling Ratesto 400 Mbpsor distance of data transferis dependent upon theClock Frequenciesto 400 MHz attenuation characteristicsof the media, the noise• Operates Froma Single 3.3-V Supply coupling to the environment, and other system
characteristics.)• Low-Voltage Differential Signaling With Typical
Output Voltageof 350 mV anda 100-Ω Load The intended applicationof this device and signaling Propagation Delay Time technique is for point-to-point baseband data
transmission over controlled impedance media of– SN65LVDS105– 2.2ns (Typ) approximately 100 Ω. The transmission media may– SN65LVDS104– 3.1ns (Typ) be printed-circuit board traces, backplanes,or cables. LVTTL Levels Are 5-V Tolerant• Electrically Compatible WithLVPECL, LVTTL, LVCMOS,SSTL,or HSTL Outputs• Driver Outputs Are High-ImpedanceDisabledor With VCC <1.5• Bus-Pin ESD Protection• SOIC and TSSOP Packaging
2 Applications Clock Distribution• Wireless Base Stations• Network Routers
SN65LVDS105 Logic Diagram (Positive Logic)SN65LVDS104 Logic Diagram (Positive Logic)
