SN65LVDS1050PWR ,2.7V Dual LVDS Transmitter/Receivermaximum ratings" may cause permanent damage to the device. These are stressratings only, and functi ..
SN65LVDS105D ,1 LVTTL:4 LVDS Clock Fanout Buffer SLLS396G–SEPTEMBER 1999–REVISED DECEMBER 20155 Selection Guide to LVDS RepeatersDEVICE NO. INPUTS ..
SN65LVDS105DR ,1 LVTTL:4 LVDS Clock Fanout BufferFeatures 3 DescriptionThe SN65LVDS10x are a differential line receiver and1• Receiver and Drivers M ..
SN65LVDS105PW ,1 LVTTL:4 LVDS Clock Fanout BufferElectrical Characteristics........ 613.1 Related Links.. 327.8 SN65LVDS104 Switching Characteristic ..
SN65LVDS105PWG4 ,1 LVTTL:4 LVDS Clock Fanout Buffer 16-TSSOP -40 to 85Maximum Ratings(1)over operating free-air temperature range (unless otherwise noted)MIN MAX UNIT(2) ..
SN65LVDS105PWR ,1 LVTTL:4 LVDS Clock Fanout BufferBlock Diagram... 152 Applications..... 19.3 Feature Description.... 153 Description....... 19.4 Dev ..
SN74HC74ADBLE ,Dual D-Type Positive-Edge-Triggered Flip-Flops With Clear and PresetLogic Diagram (Positive Logic)PRECCLKCQC TGCCCCTGD TGTGQCCCCLR1An IMPORTANT NOTICE at the end of th ..
SN74HC74D ,Dual D-Type Positive-Edge-Triggered Flip-Flops With Clear and PresetMaximum Ratings.. 411.1 Layout Guidelines.... 136.2 ESD Ratings ...... 411.2 Layout Example....... ..
SN74HC74DBR ,Dual D-Type Positive-Edge-Triggered Flip-Flops With Clear and PresetElectrical Characteristics....... 512.2 Related Links.. 146.6 Timing Requirements... 612.3 Communit ..
SN74HC74DBR ,Dual D-Type Positive-Edge-Triggered Flip-Flops With Clear and PresetFeatures 3 DescriptionThe SNx4HC74 devices contain two independent D-1• Wide Operating Voltage Rang ..
SN74HC74DR ,Dual D-Type Positive-Edge-Triggered Flip-Flops With Clear and PresetLogic Diagram (Positive Logic)PRECCLKCQC TGCCCCTGD TGTGQCCCCLR1An IMPORTANT NOTICE at the end of th ..
SN74HC74DRG4 ,Dual D-Type Positive-Edge-Triggered Flip-Flops With Clear and Preset 14-SOIC -40 to 85Logic Diagram (Positive Logic)PRECCLKCQC TGCCCCTGD TGTGQCCCCLR1An IMPORTANT NOTICE at the end of th ..
SN65LVDS1050PW-SN65LVDS1050PWR
2.7V Dual LVDS Transmitter/Receiver
www.ti.comGND
VCC
SN65LVDS1050PW(Marked as DL1050 or LDS1050)
(TOP VIEW) 1Y9 1A
DRIVER FUNCTION TABLE
RECEIVER FUNCTION TABLE
INPUTS OUTPUTS
INPUTS OUTPUT Y
VID = VA - VBVID ≥ 100 mV
-100 mV < VID < 100 mV
VID ≤ -100 mV
Open
ROpen
L H HL
H = high level, L = low level, Z = high impedance,
X = don’t care
H = high level, L = low level, Z = high impedance,
X = don’t care
SN65LVDS1050SLLS343BAPRIL1999REVISEDAPRIL 2003
HIGH-SPEED DIFFERENTIAL LINE DRIVERS AND RECEIVERS
FEATURES Typically Meets or Exceeds ANSI
TIA/EIA-644-1995 Standard Operates Froma Single 2.4-Vto 3.6-V Supply Signaling Rates upto 400 Mbit/s Bus-Terminal ESD Exceeds12 kV Low-Voltage Differential Signaling With Typi-
cal Output Voltages of 285 mV anda 100-W
Load Propagation Delay Times·
Driver: 1.7-ns Typical Receiver: 3.7-ns Typical Driver: 25-mW Typical Receiver: 60-mW Typical Power Dissipationat 200 MHz·
Driver: 25-mW Typical Receiver: 60-mW Typical LVTTL Input Levels Are 5-V Tolerant Receiver Maintains High Input Impedance Receiver Has Open-Circuit Fail Safe Available in Thin Shink Outline Packaging
With 20-mil Lead Pitch
DESCRIPTIONThe SN65LVDS1050is similarto the SN65LVDS050
except thatitis characterizedfor operation witha lower
supply voltage range and packagedin the thin shrink
outline package for portable battery-powered appli-
cations.
The differential line drivers and receivers use low-voltage differential signaling (LVDS)to achieve signaling ratesas
highas 400 Mbps. The drivers providea minimum differential output voltage magnitudeof 247 mV intoa 100-W load
and receiptof 100-mV signals withupto1Vof ground potential difference betweena transmitter and receiver.
The intended applicationof this device and signaling techniqueis for point-to-point baseband data transmission
over controlled impedance mediaof approximately 100-W characteristic impedance. The transmission media may printed-circuit board traces, backplanes,or cables. Note: The ultimate rate and distanceof data transferis
dependent upon the attenuation characteristicsof the media, the noise couplingto the environment and other
application-specific characteristics.
The SN65LVDS1050is characterizedfor operation from -40°Cto 85°C.
Pleasebe awarethat animportantnoticeconcerningavailability, standard warranty,and usein critical applicationsofTexasInstruments
semiconductor productsand disclaimersthereto appearsat theendofthis datasheet.
