SN65LVDS101DGKR ,2Gbps LVDS/LVPECL/CML to LVPECL Repeater/TranslatorTable of Contents10.2 Functional
SN65LVDS101DGKRG4 ,2Gbps LVDS/LVPECL/CML to LVPECL Repeater/Translator 8-VSSOP -40 to 85Features... 110.3 Feature Description.. 152 Applications..... 110.4 Device Functional Modes.. 203 D ..
SN65LVDS101DR ,2Gbps LVDS/LVPECL/CML to LVPECL Repeater/TranslatorMaximum Ratings.. 413.2 Layout Example....... 328.2 ESD Ratings........ 414 Device and Documentatio ..
SN65LVDS104D ,1:4 LVDS Clock Fanout BufferFeatures 3 DescriptionThe SN65LVDS10x are a differential line receiver and1• Receiver and Drivers M ..
SN65LVDS104DRG4 ,1:4 LVDS Clock Fanout Buffer 16-SOIC -40 to 85Block Diagram... 152 Applications..... 19.3 Feature Description.... 153 Description....... 19.4 Dev ..
SN65LVDS104PW ,1:4 LVDS Clock Fanout BufferMaximum Ratings(1)over operating free-air temperature range (unless otherwise noted)MIN MAX UNIT(2) ..
SN74HC7032NSR , QUADRUPLE POSITIVE-OR GATES WITH SCHMITT-TRIGGER INPUTS
SN74HC7032NSR , QUADRUPLE POSITIVE-OR GATES WITH SCHMITT-TRIGGER INPUTS
SN74HC74 ,Dual D-Type Positive-Edge-Triggered Flip-Flops With Clear and PresetMaximum Ratings(1)over operating free-air temperature range (unless otherwise noted)MIN MAX UNITV S ..
SN74HC74ADBLE ,Dual D-Type Positive-Edge-Triggered Flip-Flops With Clear and PresetLogic Diagram (Positive Logic)PRECCLKCQC TGCCCCTGD TGTGQCCCCLR1An IMPORTANT NOTICE at the end of th ..
SN74HC74D ,Dual D-Type Positive-Edge-Triggered Flip-Flops With Clear and PresetMaximum Ratings.. 411.1 Layout Guidelines.... 136.2 ESD Ratings ...... 411.2 Layout Example....... ..
SN74HC74DBR ,Dual D-Type Positive-Edge-Triggered Flip-Flops With Clear and PresetElectrical Characteristics....... 512.2 Related Links.. 146.6 Timing Requirements... 612.3 Communit ..
SN65LVDS101D-SN65LVDS101DG4-SN65LVDS101DGK-SN65LVDS101DGKG4-SN65LVDS101DGKR-SN65LVDS101DGKRG4-SN65LVDS101DR
2Gbps LVDS/LVPECL/CML to LVPECL Repeater/Translator
FUNCTIONAL DIAGRAM
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SN65LVDS100 and SN65LVDS101
SN65LVDT100 and SN65LVDT101Product
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SN65LVDS100, SN65LVDT100, SN65LVDS101, SN65LVDT101SLLS516E –AUGUST 2002–REVISED JULY 2015
SN65LVDx10x Differential Translator/Repeater Features 3 DescriptionThe SN65LVDS100, SN65LVDT100, SN65LVDS101, Designedfor Signaling Rates≥2 Gbps and SN65LVDT101 are high-speed differential• Total Jitter<65ps receivers and drivers connected as repeaters. The• Low-Power Alternativefor the MC100EP16 receiver accepts low-voltage differential signaling
(LVDS), positive-emitter-coupled logic (PECL), or• Low 100-ps (Maximum) Part-to-Part Skew current-mode logic (CML) input signalsat rates upto• 25 mVof Receiver Input Threshold Hysteresis 2 Gbps and repeatsit as either an LVDSor PECLOver 0-Vto 4-V Input Voltage Range output signal. The signal path through the deviceis• Inputs Electrically Compatible With
CML, and LVDS Signal Levels 3.3-V Supply Operation• LVDT Integrates 110-Ω Terminating• Offeredin SOIC and MSOP
2 Applications• Wireless Infrastructure• Telecom Infrastructure• Printers
