SN65CML100DRG4 ,1.5-Gbps LVDS/LVPECL/CML-to-CML Translator/Repeater 8-SOIC -40 to 85maximum ratings may cause permanent damage to the device. These are stress ratingsonly, and functio ..
SN65EL16D ,5.0 V ECL Differential Buffer 8-SOIC -40 to 85........ SLLS921–NOVEMBER 2008(1) (2)PECL DC CHARACTERISTICS (V = 5 V; V = 0 V)CC EEPARAMETER –40°C ..
SN65EL16DGKR ,5.0 V ECL Differential Buffer 8-VSSOP -40 to 85FEATURESPINOUT ASSIGNMENT• Differential PECL/NECL Receiver• Operating RangeD-8, DGK-8 Package(Top V ..
SN65ELT20D ,5V TTL to Differential PECL Translator 8-SOIC -40 to 85 SLLS922A –DECEMBER 2008–REVISED MARCH 2012(1) (2)PECL DC CHARACTERISTICS (V = 5 V; GND = 0 V)CC–40 ..
SN65ELT20DR ,5V TTL to Differential PECL Translator 8-SOIC -40 to 85FEATURESPINOUT ASSIGNMENT• 1.25-ns Maximum Propagation DelayD-8, DGK-8 Package• Operating Range: V ..
SN65ELT21DR ,5V PECL to TTL Translator 8-SOIC -40 to 85. SLLS923–JUNE 2009PECL DC CHARACTERISTICS(1)(2)At V = 5.0 V, GND = 0.0 V (unless otherwise noted)C ..
SN74HC273N. ,Octal D-Type Flip-Flops With ClearSample & Support &Product Tools &TechnicalCommunityBuyFolder Documents SoftwareSN54HC273,SN74HC273S ..
SN74HC273NSR ,Octal D-Type Flip-Flops With ClearMaximum Ratings(1)over operating free-air temperature range (unless otherwise noted)MIN MAX UNITV S ..
SN74HC273NSRG4 ,Octal D-Type Flip-Flops With Clear 20-SO -40 to 85Features 3 DescriptionThe SNx4HC273 devices are positive-edge-triggered1• Wide Operating Voltage Ra ..
SN74HC273PW ,Octal D-Type Flip-Flops With ClearMaximum Ratings(1)over operating free-air temperature range (unless otherwise noted)MIN MAX UNITV S ..
SN74HC273PWR ,Octal D-Type Flip-Flops With ClearLogic Diagram, Each Flip-Flop (Positive Logic)CCDTGTGQCCCCTGCLK(I)TGCCCCRCopyright 2016, Texas Ins ..
SN74HC273PWRG4 ,Octal D-Type Flip-Flops With Clear 20-TSSOP -40 to 85 SCLS136E–DECEMBER 1982–REVISED JULY 20165 Pin Configuration and FunctionsJ, W, DB, DW N, NS, or PW ..
SN65CML100-SN65CML100D-SN65CML100DGK-SN65CML100DGKR-SN65CML100DGKRG4-SN65CML100DR-SN65CML100DRG4
1.5-Gbps LVDS/LVPECL/CML-to-CML Translator/Repeater
www.ti.com
FEATURES DESCRIPTION
APPLICATIONS
FUNCTIONAL DIAGRAM
VCC
VBB
EYE PATTERN
1.5 Gbps
223-1 PRBS
750 MHz
VCC = 3.3 V, TA = 25°C, VID = 200 mV, VIC = 1.2 V, VTT = 3.3 V, RT = 50 Ω
Vertical Scale = 500 mV/div
Horizontal Scale = 200 ps/div
SN65CML100
SLLS547–NOVEMBER 2002
1.5-Gbps LVDS/LVPECL/CML-TO-CML TRANSLATOR/REPEATER Provides Level Translation From LVDSor This high-speed translator/repeateris designed for
LVPECLto CML, Repeating From CMLto CML signaling rates upto 1.5 Gbpsto support various
high-speed network routing applications. The driver•
Signaling Rates(1) upto 1.5 Gbpsoutputis compatible with current-mode logic (CML)•
CML Compatible Output Directly Drives levels, and directly drives 50-Ω or 25-Ω loads
Devices With 3.3-V, 2.5-V,or 1.8-V Supplies connectedto 1.8-V, 2.5-V,or 3.3-V nominal supplies.•
Total Jitter<70ps The capability for direct connectionto the loads may•
Low 100 ps (Max)•
Wide Common-ModeAllows Direct•
25 mVof Receiver
Over 0-Vto 4-V•
Propagation distortion.•
3.3-V Supply OperationThe VBB pinis an internally generated voltage supply•
Availablein SOIC and MSOP Packages LVPECL input.•
Level Translation•
622-MHz Central Office Clock Distribution•
High-Speed Network Routing•
Wireless Basestations for•
Low Jitter Clock Repeater(1)(1) The signaling rateofa lineisthe numberof voltage
transitions thatare madeper second expressedinthe units
bps (bitsper second).
