SN74LS74N ,DUAL D-TYPE POSITIVE EDGE-TRIGGERED FLIP-FLOP
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SN54LS74-SN54LS74J-SN74LS74N
Dual Positive-Edge-Triggered D Flip-Flops with Preset/ Clear and Complementary Outputs
DUAL D-TYPE POSITIVE
EDGE-TRIGGERED FLIP-FLOPThe SN54/74LS74A dual edge-triggered flip-flop utilizes Schottky TTL cir-
cuitry to produce high speed D-type flip-flops. Each flip-flop has individual
clear and set inputs, and also complementary Q and Q outputs.
Information at input D is transferred to the Q output on the positive-going
edge of the clock pulse. Clock triggering occurs at a voltage level of the clock
pulse and is not directly related to the transition time of the positive-going
pulse. When the clock input is at either the HIGH or the LOW level, the D input
signal has no effect.
LOGIC DIAGRAM (Each Flip-Flop)SET (SD) 4 (10)
CLEAR (CD) 1 (13)
CLOCK3 (11)
2 (12)
6 (8)
MODE SELECT — TRUTH TABLE Both outputs will be HIGH while both SD and CD are LOW, but the output states are unpredictable
if SD and CD go HIGH simultaneously. If the levels at the set and clear are near VIL maximum then
we cannot guarantee to meet the minimum level for VOH.
H, h = HIGH Voltage Level
L, I = LOW Voltage Level
X = Don’t Care
i, h (q) = Lower case letters indicate the state of the referenced input (or output) one set-up time
i, h (q) = prior to the HIGH to LOW clock transition.
