SN74LS73N ,DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP
SN74LS74A ,LOW POWER SCHOTTKYlogic diagram (positive logic)PmOOl-:3OICLKtThis symbol is in accordance with ANSI/IEEE Std 91-1984 ..
SN74LS74AD ,LOW POWER SCHOTTKYlogic diagram (positive logic)PmOOl-:3OICLKtThis symbol is in accordance with ANSI/IEEE Std 91-1984 ..
SN74LS74ADBR ,Dual D-type pos.-edge-triggered flip-flops with preset and clearq Package Options Include Plastic "Small SN5474 . . .J PACKAGEOutline" Packages. Ceramic Chip Carri ..
SN74LS74ADR ,Dual D-type pos.-edge-triggered flip-flops with preset and clearq Package Options Include Plastic "Small SN5474 . . .J PACKAGEOutline" Packages. Ceramic Chip Carri ..
SN74LS74ADRG4 ,Dual D-type pos.-edge-triggered flip-flops with preset and clear 14-SOIC 0 to 70q Package Options Include Plastic "Small SN5474 . . .J PACKAGEOutline" Packages. Ceramic Chip Carri ..
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SP233AEP-L , Enhanced RS-232 Line Drivers/Receivers
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SP234ACT , 5V Powered Multi-Channel RS-232 Drivers/Receivers
SP234ACT , 5V Powered Multi-Channel RS-232 Drivers/Receivers
SP235AEP , 5V Powered Multi-Channel RS-232 Drivers/Receivers
SN54LS73J-SN74LS73N
Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops with Clear and Complementary Outputs
DUAL JK NEGATIVE
EDGE-TRIGGERED FLIP-FLOPThe SN54LS/74LS73A offers individual J, K, clear, and clock inputs. These
dual flip-flops are designed so that when the clock goes HIGH, the inputs are
enabled and data will be accepted. The logic level of the J and K inputs may
be allowed to change when the clock pulse is HIGH and the bistable will per-
form according to the truth table as long as minimum set-up times are ob-
served. Input data is transferred to the outputs on the negative-going edge of
the clock pulse.
LOGIC DIAGRAM (Each Flip-Flop)13 (8)
3 (10)
12 (9)
CLEAR
2 (6)
14 (7)
1 (15)
CLOCK (CP)
MODE SELECT — TRUTH TABLEH, h = HIGH Voltage Level
L, I = LOW Voltage Level
X = Don’t Care
l, h (q) = Lower case letters indicate the state of the referenced input (or output) one set-up time
l, h (q) = prior to the HIGH to LOW clock transition.
