SN54LS114J ,DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP
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SN74GTL1655DGGRG4 , 16-BIT LVTTL-TO-GTL/GTL UNIVERSAL BUS TRANSCEIVER WITH LIVE INSERTION
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SN74GTL16612DGGR ,18-Bit LVTTL-to-GTL/GTL+ Universal Bus TransceiversFEATURESSN54GTL16612. . . WD PACKAGE• Members of Texas Instruments Widebus™SN74GTL16612. . . DGG OR ..
SN54LS114J
DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP
DUAL JK NEGATIVE
EDGE-TRIGGERED FLIP-FLOPThe SN54/74LS114A offers common clock and common clear inputs and
individual J, K, and set inputs. These monolithic dual flip-flops are designed
so that when the clock goes HIGH, the inputs are enabled and data will be
accepted. The logic level of the J and K inputs may be allowed to change when
the clock pulse is HIGH and the bistable will perform according to the truth
table as long as minimum set-up times are observed. Input data is transferred
to the outputs on the negative-going edge of the clock pulse.
LOGIC DIAGRAM (Each Flip-Flop)--- ----
MODE SELECT — TRUTH TABLE Both outputs will be HIGH while both SD and CD are LOW, but the output states
are unpredictable if SD and CD go HIGH simultaneously.
H, h = HIGH Voltage Level
L, I = LOW Voltage Level
X = Don’t Care
l, h (q) = Lower case letters indicate the state of the referenced input (or output)
l, h (q) = one set-up time prior to the HIGH to LOW clock transition.
