SN74LS112AN ,Dual JK negative edge-triggered flip-flopSN54/74LS112ADUAL JK NEGATIVEEDGE-TRIGGERED FLIP-FLOPThe SN54/74LS112A dual JK flip-flop
SN74LS112ANSR ,Dual J-K Negative-Edge-Triggered Flip-Flops With Clear And Preset
SN74LS112N ,DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOPSN54/74LS112ADUAL JK NEGATIVEEDGE-TRIGGERED FLIP-FLOPThe SN54/74LS112A dual JK flip-flop
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SN74LS122DR ,Retriggerable monostable multivibrator
SN74LS122DR2 ,Retriggerable Monostable Multivibrators2SN74LS122 SN74LS123LS122 FUNCTIONAL TABLE LS123 FUNCTIONAL TABLEINPUTS OUTPUTS INPUTS OUTPUTSCLEAR ..
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SNJ54LS197J , 50/30/100-MHZ PRESETTABLE DECADE OR BINARY COUNTERS/LATCHES
SNJ54LS20W ,Dual 4-Input Positive-NAND Gates
SNJ54LS21J ,Dual 4-Input Positive-AND GatesSN54LS21, SN74LS21DUAL 4-INPUT POSITIVE-AND GATESSDLS139 – APRIL 1985 – REVISED MARCH 1988Copyright ..
SNJ54LS21W ,Dual 4-Input Positive-AND GatesSN54LS21, SN74LS21DUAL 4-INPUT POSITIVE-AND GATESSDLS139 – APRIL 1985 – REVISED MARCH 1988Copyright ..
SNJ54LS240FK ,Octal Buffers And Line Drivers With 3-State OutputsLogic Diagram (Positive Logic)µ/6240, µ62401An IMPORTANT NOTICE at the end of this data sheet addre ..
SN54LS112AJ-SN74LS112AN
Dual JK negative edge-triggered flip-flop
DUAL JK NEGATIVE
EDGE-TRIGGERED FLIP-FLOPThe SN54/74LS112A dual JK flip-flop features individual J, K, clock, and
asynchronous set and clear inputs to each flip-flop. When the clock goes
HIGH, the inputs are enabled and data will be accepted. The logic level of the
J and K inputs may be allowed to change when the clock pulse is HIGH and
the bistable will perform according to the truth table as long as minimum set-up
and hold time are observed. Input data is transferred to the outputs on the
negative-going edge of the clock pulse.
LOGIC DIAGRAM (Each Flip-Flop)- ---- ----
MODE SELECT — TRUTH TABLE Both outputs will be HIGH while both SD and CD are LOW, but the output states
are unpredictable if SD and CD go HIGH simultaneously.
H, h = HIGH Voltage Level
L, I = LOW Voltage Level
X = Don’t Care
l, h (q) = Lower case letters indicate the state of the referenced input (or output)
l, h (q) = one set-up time prior to the HIGH to LOW clock transition.
