SN54LS109J ,DUAL JK POSITIVE EDGE-TRIGGERED FLIP-FLOP
SN54LS11 ,TRIPLE 3-INPUT AND GATE
SN54LS112AJ ,Dual JK negative edge-triggered flip-flopSN54/74LS112ADUAL JK NEGATIVEEDGE-TRIGGERED FLIP-FLOPThe SN54/74LS112A dual JK flip-flop
SN54LS112J ,DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOPSN54/74LS112ADUAL JK NEGATIVEEDGE-TRIGGERED FLIP-FLOPThe SN54/74LS112A dual JK flip-flop
SN54LS112J ,DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOPfeatures individual J, K, clock, andasynchronous set and clear inputs to each flip-flop. When the c ..
SN54LS113J ,DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP
SN74GTL1655 ,16-Bit LVTTL To GTL/GTL+ Universal Bus Transceivers with Live InsertionSCBS696I–JULY 1997–REVISED APRIL 2005DESCRIPTION/ORDERING INFORMATION (CONTINUED)This device is par ..
SN74GTL1655DGGR ,16-Bit LVTTL To GTL/GTL+ Universal Bus Transceivers with Live InsertionSCBS696I–JULY 1997–REVISED APRIL 2005FUNCTION TABLESABC(1)FUNCTIONINPUTSOUTPUTMODEBOEAB LEAB CLK AH ..
SN74GTL1655DGGRG4 , 16-BIT LVTTL-TO-GTL/GTL UNIVERSAL BUS TRANSCEIVER WITH LIVE INSERTION
SN74GTL16612ADGGR , 18-BIT LVTTL-TO-GTL/GTLPLUS UNIVERSAL BUS TRANSCEIVERS
SN74GTL16612ADGGR , 18-BIT LVTTL-TO-GTL/GTLPLUS UNIVERSAL BUS TRANSCEIVERS
SN74GTL16612DGGR ,18-Bit LVTTL-to-GTL/GTL+ Universal Bus TransceiversFEATURESSN54GTL16612. . . WD PACKAGE• Members of Texas Instruments Widebus™SN74GTL16612. . . DGG OR ..
SN54LS109J
DUAL JK POSITIVE EDGE-TRIGGERED FLIP-FLOP
DUAL JK POSITIVE
EDGE-TRIGGERED FLIP-FLOPThe SN54/74LS109A consists of two high speed completely independent
transition clocked JK flip-flops. The clocking operation is independent of rise
and fall times of the clock waveform. The JK design allows operation as a D
flip-flop by simply connecting the J and K pins together.
LOGIC DIAGRAM- --- ------
MODE SELECT — TRUTH TABLE Both outputs will be HIGH while both SD and CD are LOW, but the output states
are unpredictable if SD and CD go HIGH simultaneously.
H, h = HIGH Voltage Level
L, I = LOW Voltage Level
X = Don’t Care
l, h (q) = Lower case letters indicate the state of the referenced input (or output)
l, h (q) = one set-up time prior to the LOW to HIGH clock transition.
