SN54F374J ,Octal Edge-Triggered D-type Flip-Flops With 3-State Outputsmaximum ratings over operating free-air temperature range (unless otherwise noted)Supply voltage ra ..
SN54F37J , QUADRUPLE 2-INPUT POSITIVE-NAND BUFFERS
SN54F38J , QUADRUPLE 2-INPUT POSITIVE-NAND BUFFERS WITH OPEN-COLLECTOR OUTPUTS
SN54F521J ,8-Bit Identity Comparators SDFS091 − MARCH 1987 − REVISED OCTOBER 1993SN54F521 . ..
SN54F573J , OCTAL TRANSPARENT D-TYPE LATCHES WITH S0STATE OUTPUTS
SN54F74J ,Dual Positive-Edge-Triggered D-type Flip-Flops With Clear And Preset SN54F74, SN74F74 DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESETSDFS046A – MA ..
SN74F151B ,8-Line To 1-Line Data Selector/Multiplexer SDFS023A − D2932, MARCH 1987 − REVISED OCT ..
SN74F151BD ,8-Line To 1-Line Data Selector/Multiplexermaximum ratings over operating free-air temperature range (unless otherwise noted)Supply voltage ra ..
SN74F151BDR ,8-Line To 1-Line Data Selector/Multiplexer SDFS023A − D2932, MARCH 1987 − REVISED OCT ..
SN74F151BN ,8-Line To 1-Line Data Selector/Multiplexerlogic diagram (positive logic)7G4D03D12D21D35DataYInputs615WD414D513D612D711AData10BSelect(binary)9 ..
SN74F151BNSR ,8-Line To 1-Line Data Selector/Multiplexermaximum ratings over operating free-air temperature range (unless otherwise noted)Supply voltage ra ..
SN74F153DR ,Dual 1-of-4 Data Selectors/Multiplexersmaximum ratings over operating free-air temperature range (unless otherwise noted)Supply voltage ra ..
SN54F374J-SNJ54F374J
Octal Edge-Triggered D-type Flip-Flops With 3-State Outputs
Package Options Include PlasticSmall-Outline (SOIC) and Shrink
Small-Outline (SSOP) Packages, Ceramic
Chip Carriers, and Plastic and Ceramic
DIPs
descriptionThese 8-bit flip-flops feature 3-state outputs
designed specifically for driving highly capacitive
or relatively low-impedance loads. They are
particularly suitable for implementing buffer
registers, I/O ports, bidirectional bus drivers, and
working registers.
The eight flip-flops of the ′F374 are edge-triggered
D-type flip-flops. On the positive transition of the
clock (CLK) input, the Q outputs are set to the logic
levels that were set up at the data (D) inputs.
A buffered output enable (OE) input can be used
to place the eight outputs in either a normal logic
state (high or low) or a high-impedance state. In
the high-impedance state, the outputs neither
load nor drive the bus lines significantly. The
high-impedance state and the increased drive
provide the capability to drive bus lines without
need for interface or pullup components.
The output enable (OE) input does not affect internal operations of the flip-flop. Old data can be retained or new
data can be entered while the outputs are in the high-impedance state.
The SN74F374 is available in TI’s shrink small-outline package (DB), which provides the same I/O pin count
and functionality of standard small-outline packages in less than half the printed-circuit-board area.
The SN54F374 is characterized for operation over the full military temperature range of −55°C to 125°C. The
SN74F374 is characterized for operation from 0°C to 70°C.
FUNCTION TABLE
(each flip-flop)
