SN54AS573AJ ,Octal D-type Transparent Latches With 3-State Outputs SDAS048D ..
SN54AS574J ,Octal D-type Edge-Triggered Flip-Flops With 3-State Outputs SN54ALS574B, SN54AS574, SN54AS575 SN74ALS574B, SN74ALS575A, SN74AS574, SN74AS575 OCTAL D-TYPE EDGE ..
SN54AS645J ,Octal Bus Transceivers With 3-State Outputs SN54ALS645A, SN54AS645, SN74ALS645A, SN74AS645 OCTAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS SDAS278 ..
SN54AS645J ,Octal Bus Transceivers With 3-State Outputselectrical characteristics over recommended operating free-air temperature range (unlessotherwise n ..
SN54AS646JT , OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS
SN54AS652JT ,Octal Bus Transceivers And Registers With 3-State Outputs SN54ALS652, SN54ALS653, SN54AS651, SN54AS652 SN74ALS651A, SN74ALS652A, SN74ALS653, SN74ALS654, SN7 ..
SN74F02N ,Quad 2-input positive-NOR gatesmaximum ratings” may cause permanent damage to the device. These are stress ratings only andfunctio ..
SN74F02NSR ,Quad 2-input positive-NOR gateslogic diagram (positive logic)21A 11Y31B52A 42Y62B83A1093Y3B114A1312 4Y4BPin numbers shown are for ..
SN74F04 ,Hex invertersmaximum ratings” may cause permanent damage to the device. These are stress ratings only andfunctio ..
SN74F04D ,Hex invertersmaximum ratings” may cause permanent damage to the device. These are stress ratings only andfunctio ..
SN74F04DR ,Hex invertersmaximum ratings” may cause permanent damage to the device. These are stress ratings only andfunctio ..
SN74F04N ,Hex invertersmaximum ratings over operating free-air temperature range (unless otherwise noted)Supply voltage ra ..
SN54AS573AJ
Octal D-type Transparent Latches With 3-State Outputs
Package Options Include PlasticSmall-Outline (DW) Packages, Ceramic
Chip Carriers (FK), Standard Plastic (N) and
Ceramic (J) 300-mil DIPs, and Ceramic Flat
(W) Packages
descriptionThese octal D-type transparent latches feature
3-state outputs designed specifically for driving
highly capacitive or relatively low-impedance
loads. They are particularly suitable for
implementing buffer registers, I/O ports,
bidirectional bus drivers, and working registers.
While the latch-enable (LE) input is high, outputs
(Q) respond to the data (D) inputs. When LE is low,
the outputs are latched to retain the data that was
set up.
A buffered output-enable (OE) input can be used
to place the eight outputs in either a normal logic
state (high or low) or a high-impedance state. In
the high-impedance state, the outputs neither load
nor drive the bus lines significantly. The
high-impedance state and the increased drive
provide the capability to drive bus lines without
interface or pullup components.
OE does not affect internal operation of the
latches. Old data can be retained or new data can
be entered while the outputs are in the
high-impedance state.
The SN54ALS573C and SN54AS573A are characterized for operation over the full military temperature range
of −55°C to 125°C. The SN74ALS573C and SN74AS573A are characterized for operation from 0°C to 70°C.
FUNCTION TABLE
(each latch)
