SN54ALS273J ,Octal D-type Flip-Flops With Clearmaximum ratings” may cause permanent damage to the device. These are stress ratings only, andfuncti ..
SN54ALS299J , 8-BIT UNIVERSAL SHIFT/STORAGE REGISTERS WITH 3-STATE OUTPUTS
SN54ALS32J ,Quadruple 2-Input Positive-OR Gatesmaximum ratings” may cause permanent damage to the device. These are stress ratings only, andfuncti ..
SN54ALS33AJ ,Quadruple 2-Input Positive-NOR Buffers With Open-Colector Outputselectrical characteristics over recommended operating free-air temperature range (unlessotherwise n ..
SN54ALS352J ,DUAL 4-LINE TO 1-LINE DATA SELECTORS/MULTIPLEXERS
SN54ALS373AJ ,Octal D-Type Transparent Latches with 3-state Outputs SN54ALS373A, SN54AS373, SN74ALS373A, SN74AS373 OCTAL TRANSPARENT D-TYPE LATCHESWITH 3-STATE OUTPUT ..
SN74CBTLV3384DGVR ,Low-Voltage 10-Bit FET Bus SwitchSN74CBTLV3384LOW-VOLTAGE 10-BIT FET BUS SWITCHSCDS059G − MARCH 1998 − REVISED JUNE 2004DBQ, DGV, DW ..
SN74CBTLV3384PW ,Low-Voltage 10-Bit FET Bus Switch/sc/package.FUNCTION TABLE(each 5-bit bus switch)INPUTS INPUTS/OUTPUTS1OE 2OE 1B1−1B5 2B1−2B5L L 1A ..
SN74CBTLV3384PWR ,Low-Voltage 10-Bit FET Bus Switchmaximum ratings over operating free-air temperature range (unless otherwise noted)Supply voltage ra ..
SN74CBTLV3861DBQR ,Low-Voltage 10-Bit FET Bus Switchlogic diagram (positive logic)2 22A1 SW B11113A10 SW B1023OEsimplified schematic, each FET switchA ..
SN74CBTLV3861DGVR ,Low-Voltage 10-Bit FET Bus Switchmaximum ratings” may cause permanent damage to the device. These are stress ratings only, andfuncti ..
SN74CBTLV3861DWR ,Low-Voltage 10-Bit FET Bus Switchmaximum ratings over operating free-air temperature range (unless otherwise noted)Supply voltage ra ..
SN54ALS273J-SNJ54ALS273J
Octal D-type Flip-Flops With Clear
Applications Include:Buffer/Storage Registers
Shift Registers
Pattern Generators Package Options Include Plastic
Small-Outline (DW) Packages, Ceramic
Chip Carriers (FK), and Standard Plastic (N)
and Ceramic (J) 300-mil DIPs
descriptionThese octal positive-edge-triggered flip-flops
utilize TTL circuitry to implement D-type flip-flop
logic with a direct-clear (CLR) input.
Information at the data (D) inputs meeting the
setup-time requirements is transferred to the
Q outputs on the positive-going edge of the clock
(CLK) pulse. Clock triggering occurs at a particular
voltage level and is not directly related to the
transition time of the positive-going pulse. When
CLK is at either the high or low level, the D input
signal has no effect at the output.
The SN54ALS273 is characterized for operation
over the full military temperature range of –55°C
to 125°C. The SN74ALS273 is characterized for
operation from 0°C to 70°C.
FUNCTION TABLE
(each flip-flop)GND
CLK1QCLR5D
GND
CLK
SN54ALS273... FK PACKAGE
(TOP VIEW)
