SN54ALS174J ,Hex D-type Flip-Flops With Clear/sc/package.‡This orderable is not recommended for new designs.FUNCTION TABLE(each flip-flop)INPUTS ..
SN54ALS175J ,Quadruple D-type Flip-Flops With Clear SN54ALS174, SN54ALS175, SN54AS174, SN54AS175B SN74ALS174, SN74ALS175, SN74AS174, SN74AS175BHEX/QUA ..
SN54ALS193AJ. ,Synchronous 4-Bit Up/Down Binary Counters With Dual Clock SDAS211C − DECE ..
SN54ALS20AJ , DUAL 4-INPUT POSITIVE-NAND GATES
SN54ALS21AJ ,Dual 4-Input Positive-AND Gates SDAS085B − APRIL 1982 − REVISE ..
SN54ALS244CJ ,Octal Buffers And Line Drivers With 3-State Outputselectrical characteristics over recommended operating free-air temperature range (unlessotherwise n ..
SN74CBTLV3253RGYR ,Low-Voltage Dual 1-of-4 FET Multiplexer/DemultiplexerBlock Diagram..... 84 Revision HistoryNOTE: Page numbers for previous revisions may differ from pag ..
SN74CBTLV3257D ,Low-Voltage 4-Bit 1-Of-2 FET Multiplexer/DemultiplexerMaximum Ratings(1)over operating free-air temperature range (unless otherwise noted)MIN MAX UNITV S ..
SN74CBTLV3257D ,Low-Voltage 4-Bit 1-Of-2 FET Multiplexer/DemultiplexerElectrical Characteristics....... 512.3 Community Resources...... 116.6 Switching Characteristics.. ..
SN74CBTLV3257DBQR ,Low-Voltage 4-Bit 1-Of-2 FET Multiplexer/DemultiplexerMaximum Ratings.. 411.2 Layout Example....... 106.2 ESD Ratings........ 412 Device and Documentatio ..
SN74CBTLV3257DGVR ,Low-Voltage 4-Bit 1-Of-2 FET Multiplexer/DemultiplexerMaximum Ratings.. 4J• Changed wording in Detailed Design Procedure to clarify device operation. 9• ..
SN74CBTLV3257DR ,Low-Voltage 4-Bit 1-Of-2 FET Multiplexer/DemultiplexerSample & Support &Product Tools &TechnicalCommunityBuyFolder Documents SoftwareSN74CBTLV3257SCDS040 ..
SN54ALS174-SN54ALS174J-SNJ54ALS-174FK-SNJ54ALS174J
Hex D-type Flip-Flops With Clear
Isolation From External Disturbances
(’AS Only)
SN54ALS175 ...J OR W PACKAGE
SN54AS175B ...J PACKAGE
SN74ALS175, SN74AS175B... D, N, OR NS PACKAGE
(TOP VIEW)
SN54ALS174 ...J OR W PACKAGE
SN54AS174 ...J PACKAGE
SN74ALS174, SN74AS174 ...D , N, OR NS PACKAGE
(TOP VIEW)
SN54ALS174, SN54AS174... FK PACKAGE
(TOP VIEW)CLRNC
CLK
GND
NC – No internal connection
CLR
GND
VCC
CLK
SN54ALS175... FK PACKAGE
(TOP VIEW)CLRNC
CLK
GND
CLR
GNDCC
CLK
descriptionThese positive-edge-triggered flip-flops utilize TTL circuitry to implement D-type flip-flop logic. All have a
direct-clear (CLR) input. The ’ALS175 and ’AS175B feature complementary outputs from each flip-flop.
Information at the data (D) inputs meeting the setup-time requirements is transferred to the outputs on the
positive-going edge of the clock pulse. Clock triggering occurs at a particular voltage level and is not directly
related to the transition time of the positive-going pulse. When the clock (CLK) input is at either the high or low
level, the D-input signal has no effect at the output.
These circuits are fully compatible for use with most TTL circuits.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
