SMP18 ,Fast Acquisition Octal Sample-and-Hold with Multiplexed InputSpecifications subject to change without notice.–2–REV. CSMP18ABSOLUTE MAXIMUM RATINGSPIN CONNECTIO ..
SMP18FP ,Octal Sample-and-Hold with Multiplexed InputGENERAL DESCRIPTIONSW 2 CH OUT6The SMP18 is a monolithic octal sample-and-hold; it has eightinterna ..
SMP18FS ,Octal Sample-and-Hold with Multiplexed InputSpecifications subject to change without notice.–2–REV. CSMP18ABSOLUTE MAXIMUM RATINGSPIN CONNECTIO ..
SMP30-100 ,TRISILFEATURESn Bidirectional crowbar protectionn Voltage range from 62V to 270Vn Low capacitance from 12 ..
SMP30-120 ,TRISILAPPLICATIONSTelecommunication equipment such asn Analog and digital line cards (xDSL, T1/E1,SCHEMAT ..
SMP30-130 ,TRISILFEATURESn Bidirectional crowbar protectionn Voltage range from 62V to 270Vn Low capacitance from 12 ..
SN74ALS832A ,Hex 2-Input OR Driverselectrical characteristics over recommended operating free-air temperature range (unlessotherwise n ..
SN74ALS832AN ,Hex 2-Input OR Drivers SN54ALS832A, SN54AS832B, SN74ALS832A, SN74AS832B HEX 2-INPUT OR DRIVERS SDAS017C – DECEMBER 1982 ..
SN74ALS843NT , 9-BIT BUS-INTERFACE D-TYPE LATCH WITH 3-STATE OUTPUTS
SN74ALS845-1NT , 8-BIT BUS-INTERFACE D-TYPE LATCHES WITH 3-STATE OUTPUTS
SN74ALS857DW , HEX 2-TO-1 UNIVERSAL MULTIPLEXERS WITH 3-STATE OUTPUTS
SN74ALS86 ,Quadruple 2-Input Exclusive-OR Gatesmaximum ratings over operating free-air temperature range (unless otherwise noted)Supply voltage, V ..
SMP18
Fast Acquisition Octal Sample-and-Hold with Multiplexed Input
REV.C
Octal Sample-and-Hold
with Multiplexed Input
FUNCTIONAL BLOCK DIAGRAM
DGND
VDD
CH0OUT
CH1OUT
CH2OUT
CH3OUT
CH4OUT
CH5OUT
CH6OUT
CH7OUT
VSS
INPUT
(LSB)B
(MSB)INH
FEATURES
High Speed Version of SMP08
Internal Hold Capacitors
Low Droop Rate
TTL/CMOS Compatible Logic Inputs
Single or Dual Supply Operation
Break-Before-Make Channel Addressing
Compatible With CD4051 Pinout
Low Cost
APPLICATIONS
Multiple Path Timing Deskew for A.T.E.
Memory Programmers
Mass Flow/Process Control Systems
Multichannel Data Acquisition Systems
Robotics and Control Systems
Medical and Analytical Instrumentation
Event Analysis
Stage Lighting Control
GENERAL DESCRIPTIONThe SMP18 is a monolithic octal sample-and-hold; it has eight
internal buffer amplifiers, input multiplexer, and internal hold
capacitors. It is manufactured in an advanced oxide isolated
CMOS technology to obtain high accuracy, low droop rate, and
fast acquisition time. The SMP18 has a typical linearity error of
only 0.01% and can accurately acquire a 10-bit input signal to
±1/2 LSB in less than 2.5 microseconds. The SMP18’s output
swing includes the negative supply in both single and dual sup-
ply operation.
The SMP18 was specifically designed for systems that use a
calibration cycle to adjust a multiple of system parameters. The
low cost and high level of integration make the SMP18 ideal for
calibration requirements that have previously required an ASIC,
or high cost multiple D/A converters.
The SMP18 is also ideally suited for a wide variety of sample-
and-hold applications including amplifier offset or VCA gain ad-
justments. One or more SMP18s can be used with single or
multiple DACs to provide multiple set points within a system.
The SMP18 offers significant cost and size reduction over
discrete designs. It is available in a 16-pin plastic DIP, a
narrow body SO-16 surface-mount SOIC package or the thin
TSSOP-16 package. The SMP18 is a higher speed direct
replacement for the SMP08.
ELECTRICAL CHARACTERISTICS
ELECTRICAL CHARACTERISTICSNOTES
SMP18–SPECIFICATIONS
(@ VDD = +5 V, VSS = –5 V, DGND = 0 V, RL = No Load, TA = –408C to +858C for SMP18F,
unless otherwise noted)
(@ VDD = +12 V, VSS = 0 V, DGND = 0 V, RL = No Load, TA = –408C to +858C for SMP18F,
unless otherwise noted)
PIN CONNECTIONS
ORDERING GUIDE
ABSOLUTE MAXIMUM RATINGSVDD to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . .–0.3 V, 17 V
VDD to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .–0.3 V, 17 V
VLOGIC to DGND . . . . . . . . . . . . . . . . . . . . . . . .–0.3 V, VDD
VIN to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VSS, VDD
VOUT to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VSS, VDD
Analog Output Current . . . . . . . . . . . . . . . . . . . . . . .±20 mA
(Not short-circuit protected)
Operating Temperature Range
FP, FS . . . . . . . . . . . . . . . . . . . . . . . . . . . .–40°C to +85°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . .+150°C
Storage Temperature . . . . . . . . . . . . . . . . . .–65°C to +150°C
Lead Temperature (Soldering, 60 sec) . . . . . . . . . . . .+300°C
NOTES
*θJA is specified for worst case mounting conditions, i.e., θJA is specified for device
in socket for plastic DIP packages; θJA is specified for device soldered to printed
circuit board for SOIC and TSSOP packages.
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the SMP18 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
SMP18
TEMPERATURE – °C
DROOP RATE – mV/s
0.1Droop Rate vs. Temperature
INPUT VOLTAGE – Volts
HOLD STEP – mV1023456789Hold Step vs. Input Voltage
INPUT VOLTAGE – Volts
OFFSET VOLTAGE – mV
–101023456789Offset Voltage vs. Input Voltage
–Typical Performance Characteristics
INPUT VOLTAGE – Volts
DROOP RATE – mV/s1023456789Droop Rate vs. Input Voltage
TEMPERATURE – °C
HOLD STEP – mV
–55–35125–15525658510545Hold Step vs. Temperature
INPUT VOLTAGE – Volts
OFFSET VOLTAGE – mV
–10Offset Voltage vs. Input Voltage
Droop Rate vs. Input Voltage
Slew Rate vs. VDD
Offset Voltage vs. Input Voltage
TEMPERATURE – °C
OFFSET VOLTAGE – mV
–55–35125–15525658510545Offset Voltage vs. Temperature
VDD – Volts
SUPPLY CURRENT – mA18810121416Supply Current vs. VDD
Sample Mode Power Supply Rejection
FREQUENCY – Hz
GAIN – dB
1001k10M10k100k1M
PHASE SHIFT – DegreesGain, Phase Shift vs. Frequency
FREQUENCY – Hz
PEAK-TO-PEAK OUTPUT – Volts
10k100k10M1MMaximum Output Voltage vs.
Frequency
FREQUENCY – Hz
OUTPUT IMPEDANCE – 101001M1k10k100kOutput Impedance vs. Frequency
Hold Mode Power Supply Rejection
SMP18
VCC
+15V
10kΩ
10kΩBurn-in Circuit
APPLICATIONS INFORMATIONThe SMP18, a multiplexed octal S/H, minimizes board space
in systems requiring cycled calibration or an array of control
voltages. When used in conjunction with a low cost 16-bit D/A,
the SMP18 can easily be integrated into microprocessor based
systems. Since the SMP18 features break-before-make switching
and an internal decoder, no external logic is required. The
SMP18 has an internally regulated TTL supply so that
TTL/CMOS compatibility is maintained over the full supply
range. See Figure 1 for channel decode address information.
POWER SUPPLIESThe SMP18 is capable of operating with either single or dual
supplies over a voltage range of 7 to 15 volts. Based on the sup-
ply voltages chosen, VDD and VSS establish the output voltage
range, which is:
(VSS + 0.06 V) ≤ VOUT ≤ (VDD – 2 V)
Note that several specifications, including acquisition time, off-
set and output voltage compliance, will degrade for supply volt-
ages of less than 7 V.
If split supplies are used, the negative supply should be bypassed
with a 0.1 μF capacitor in parallel with a 10 μF to ground. The
internal hold capacitors are connected to this supply pin, and
any noise will appear at the outputs.
In single supply applications, it is extremely important that the
VSS (negative supply) pin is connected to a clean ground. The
hold capacitors are internally tied to the VSS (negative) rail. Any
ground noise or disturbance will directly couple to the output of
the sample-and-hold degrading the signal-to-noise performance.
The analog and digital ground traces on the circuit board should
be physically separated to reduce digital switching noise from
entering the analog circuitry.
POWER SUPPLY SEQUENCINGVDD should be applied to the SMP18 before the logic input sig-
nals. The SMP18 has been designed to be immune to latchup,
but standard precautions should still be taken.
OUTPUT BUFFERS (Pins 1, 2, 4, 5, 12, 13, 14, 15)The buffer offset specification is 10 mV; this is less than 1/2
LSB of an 8-bit DAC with 10 V full scale. The hold step (mag-
nitude of step caused in the output voltage when switching from
sample-to-hold mode, also referred to as the pedestal error or
sample-to-hold offset) is about 4 mV with little variation over
the full output voltage range. The droop rate of a held channel
is 2 mV/s typical and 40 mV/s maximum.
The buffers are designed to drive loads connected to ground.
The outputs can source more than 20 mA over the full voltage
range but have limited current sinking capability near VSS. In
split supply operation, symmetrical output swings can be ob-
tained by restricting the output range to 2 V from either supply.
On-chip SMP18 buffers eliminate potential stability problems
associated with external buffers; outputs are stable with capaci-
tive loads up to 500 pF. However, since the SMP18’s buffer
outputs are not short circuit protected, care should be taken to
avoid shorting any output to the supplies or ground.
SIGNAL INPUT (Pin 3)The signal input should be driven from a low impedance voltage
source such as the output of an op amp. The op amp should
have a high slew rate and fast settling time if the SMP18’s ac-
quisition time characteristics are to be maintained. As with all
CMOS devices, all input voltages should be kept within range of
the supply rails (VSS ≤ VIN ≤ VDD) to avoid the possibility of
latchup. If single supply operation is desired, op amps such as
the OP183 or AD820 that have input and output voltage com-
pliances including ground, can be used to drive the inputs. Split
supplies, such as ±7.5 V, can be used with the SMP18.
