SMP04EP-SMP04EQ-SMP04ES Fast Delivery |IC PHOENIX CO.,LIMITED

SMP04ES ,CMOS Quad Sample-and-Hold AmplifierGENERAL DESCRIPTIONThe SMP04 offers significant cost and size reduction overThe SMP04 is a monolith ..
SMP04ES ,CMOS Quad Sample-and-Hold AmplifierSpecifications are subject to change without notice.REV. D–2–SMP04ABSOLUTE MAXIMUM RATINGSPackage T ..
SMP08FP ,Octal Sample-and-Hold with Multiplexed InputGENERAL DESCRIPTIONSW 4 CH OUT7The SMP08 is a monolithic octal sample-and-hold; it has eightHOLD CA ..
SMP08FS ,Octal Sample-and-Hold with Multiplexed InputSpecifications subject to change without notice.–2–REV. DSMP08ABSOLUTE MAXIMUM RATINGSORDERING GUID ..
SMP08FS ,Octal Sample-and-Hold with Multiplexed Inputapplications including amplifier offset or VCA gainadjustments. One or more SMP08s can be used with ..
SMP08FS ,Octal Sample-and-Hold with Multiplexed InputCHARACTERISTICSLogic Input High Voltage V 2.4 VINHLogic Input Low Voltage V 0.8 VINLLogic Input Cur ..
SN74ALS574BDW ,Octal D-Type Edge-Triggered Flip-Flops with 3-State Outputslogic diagrams (positive logic)SN54ALS574B, SN74ALS574B, SN74ALS575A, SN54AS575,SN54AS574, SN74AS57 ..
SN74ALS574BDWR ,Octal D-Type Edge-Triggered Flip-Flops with 3-State Outputsmaximum ratings” may cause permanent damage to the device. These are stress ratings only, andfuncti ..
SN74ALS574BN ,Octal D-Type Edge-Triggered Flip-Flops with 3-State Outputsmaximum ratings over operating free-air temperature range (unless otherwise noted)Supply voltage, V ..
SN74ALS574BNSR ,Octal D-Type Edge-Triggered Flip-Flops with 3-State Outputs SN54ALS574B, SN54AS574, SN54AS575 SN74ALS574B, SN74ALS575A, SN74AS574, SN74AS575 OCTAL D-TYPE EDGE ..
SN74ALS575ADW ,Octal D-Type Edge-Triggered Flip-Flops With 3-State Outputs SN54ALS574B, SN54AS574, SN54AS575 SN74ALS574B, SN74ALS575A, SN74AS574, SN74AS575 OCTAL D-TYPE EDGE ..
SN74ALS576BDW ,Octal D-Type Edge-Triggered Flip-Flops With 3-State Outputsmaximum ratings” may cause permanent damage to the device. These are stress ratings only, andfuncti ..

SMP04EP-SMP04EQ-SMP04ES
CMOS Quad Sample-and-Hold Amplifier
REV. DCMOS Quad
Sample-and-Hold Amplifier
FUNCTIONAL BLOCK DIAGRAM
FEATURES
Four Independent Sample-and-Holds
Internal Hold Capacitors
High Accuracy: 12 Bit
Very Low Droop Rate: 2 mV/s typ
Output Buffers Stable for CL £ 500 pF
TTL/CMOS Compatible Logic Inputs
Single or Dual Supply Applications
Monolithic Low Power CMOS Design
APPLICATIONS
Signal Processing Systems
Multichannel Data Acquisition Systems
Automatic Test Equipment
Medical and Analytical Instrumentation
Event Analysis
DAC Deglitching
The SMP04 offers significant cost and size reduction over
equivalent module or discrete designs. It is available in a
16-lead hermetic or plastic DIP and surface mount SOIC
packages. It is specified over the extended industrial tem-
perature range of –40°C to +85°C.
GENERAL DESCRIPTION
The SMP04 is a monolithic quad sample-and-hold; it has four
internal precision buffer amplifiers and internal hold capacitors.
It is manufactured in ADI’s advanced oxide isolated CMOS
technology to obtain the high accuracy, low droop rate and fast
acquisition time required by data acquisition and signal process-
ing systems. The device can acquire an 8-bit input signal to1/2 LSB in less than four microseconds. The SMP04 can
operate from single or dual power supplies with TTL/CMOS
logic compatibility. Its output swing includes the negative supply.
The SMP04 is ideally suited for a wide variety of sample-and-
hold applications, including amplifier offset or VCA gain adjust-
ments. One or more can be used with single or multiple DACs
to provide multiple setpoints within a system.
*. Patent No. 4,739,281.
SMP04–SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
ELECTRICAL CHARACTERISTICS
NOTESOutputs are capable of sinking and sourcing over 20 mA, but linearity and offset are guaranteed at specified load levels.
(@ VDD = +12.0 V, VSS = DGND = 0 V, RL = No Load, TA = Operating Temperature Range
specified in Absolute Maximum Ratings, unless otherwise noted.)
(@ VDD = +5.0 V, VSS = –5.0 V, DGND = 0.0 V, RL = No Load, TA = Operating Temperature
Range specified in Absolute Maximum Ratings, unless otherwise noted.)
ABSOLUTE MAXIMUM RATINGS
(TA = +25°C unless otherwise noted)
VDD to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . .–0.3 V, 17 V
VDD to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . .–0.7 V, 17 V
VLOGIC to DGND . . . . . . . . . . . . . . . . . . . . . . . .–0.3 V, VDD
VIN to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VSS, VDD
VOUT to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VSS, VDD
Analog Output Current . . . . . . . . . . . . . . . . . . . . . . .–20 mA
(Not Short-Circuit Protected)
Digital Input Voltage to DGND . . . . . . .–0.3 V, VDD + 0.3 V
Operating Temperature Range
EQ, EP, ES . . . . . . . . . . . . . . . . . . . . . . . .–40°C to +85°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . .+150°C
Storage Temperature . . . . . . . . . . . . . . . . . .–65°C to +150°C
Lead Temperature (Soldering, 60 sec) . . . . . . . . . . . .+300°C
*uJA is specified for worst case mounting conditions, i.e., uJA is specified for device
in socket for cerdip and plastic DIP packages; uJA is specified for device soldered
to printed circuit board for SO package.
CAUTIONStresses above those listed under Absolute Maximum Ratings may cause
permanent damage to the device. This is a stress rating only; function operation
at or above this specification is not implied. Exposure to the above maximum
rating conditions for extended periods may affect device reliability.Digital inputs and outputs are protected; however, permanent damage may
occur on unprotected units from high energy electrostatic fields. Keep units in
conductive foam or packaging at all times until ready to use. Use proper antistatic
handling procedures.Remove power before inserting or removing units from their sockets.
ORDERING GUIDE
*Q = Cerdip; N = Plastic DIP; R = Small Outline.
PIN CONNECTIONS
16-Lead Cerdip
16-Lead Plastic DIP
16-Lead SO
NC = NO CONNECT
VOUT2
VSS
VOUT4
VOUT3
VDD
VOUT1
VIN1
S/H4
VIN3
VIN4VIN2
S/H1
S/H2
DGNDS/H3
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the SMP04 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
SMP04
WAFER TEST LIMITS
NOTE
Electrical tests are performed at wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed
for standard product dice. Consult factory to negotiate specifications based on dice lot qualifications through sample lot assembly and testing.
(@ VDD = +12 V, VSS = DGND = 0 V, RL = No Load, TA = +258C, unless otherwise noted.)
Dice Characteristics
Die Size: 0.80 x 0.120 mil = 9,600 sq. mil
(2.032 x 3.048mm = 6.193 sq. mm)
Figure 2.Droop Rate vs. Input
Voltage (TA = +25°C)
Figure 5.Hold Step vs. Temperature
Figure 8.Offset Voltage vs. Input
Voltage (TA = +125°C)
Figure 3.Droop Rate vs. Input
Voltage (TA = +125°C)
Figure 6.Slew Rate vs. VDD
Figure 9.Offset Voltage vs. Input
Voltage (TA = –55°C)
Figure 1.Droop Rate vs. Temperature
Figure 4.Hold Step vs. Input Voltage
Figure 7.Offset Voltage vs. Input
Voltage (TA = +25°C)
SMP04
Figure 10.Offset Voltage vs.
Temperature
PHASE SHIFT – Degrees
Figure 13.Gain, Phase Shift vs.
Frequency
Figure 11.Supply Current vs. VDD
Figure 14.Output Impedance vs.
Frequency
Figure 12.Sample Mode
Power Supply Rejection
Figure 15.Maximum Output Voltage
vs. Frequency
GENERAL INFORMATION
The SMP04 is a quad sample-and-hold with each track-and-
hold having its own input, output, control, and on-chip hold
capacitor. The combination of four high performance track-and-
hold capacitors on a single chip greatly reduces board space and
design time while increasing reliability.
After the device selection, the primary considerations in using
track-and-holds are the hold capacitor and layout. The SMP04
eliminates most of these problems by having the hold capacitors
internal, eliminating the problems of leakage, feedthrough,
guard ring layout and dielectric absorption.
POWER SUPPLIES
The SMP04 is capable of operating with either single or dual
supplies over a voltage range of 7 to 15 volts. Based on the
supply voltages chosen, VDD and VSS establish the output volt-
age range, which is:
VSS + 0.05 V £ VOUT £ VDD –2 V
Note that several specifications, including acquisition time,
offset and output voltage compliance will degrade for a total
supply voltage of less than 7 V. Positive supply current is typi-
cally 4 mA with the outputs unloaded. The SMP04 has an inter-
nally regulated TTL supply so that TTL/CMOS compatibility
will be maintained over the full supply range.
Single Supply Operation Grounding Considerations
In single supply applications, it is extremely important that the
VSS (negative supply) pin be connected to a clean ground. This
is because the hold capacitor is internally tied to VSS. Any noise
or disturbance in the ground will directly couple to the output of
the sample-and-hold, degrading the signal-to-noise performance.
It is advisable that the analog and digital ground traces on the
circuit board be physically separated to reduce digital switching
noise from entering the analog circuitry.
Power Supply Bypassing
For optimum performance, the VDD supply pin must also be
bypassed with a good quality, high frequency ceramic capacitor.
The recommended value is 0.1 mF. In the case where dual sup-
plies are used, VSS (negative supply) bypassing is particularly
important. Again this is because the internal hold capacitor is
tied to VSS. Good bypassing prevents high frequency noise from
entering the sample-and-hold amplifier. A 0.1 mF ceramic bypass
capacitor is generally sufficient. For high noise environments,
adding a 10 mF tantalum capacitor in parallel with the 0.1 mF
provides additional protection.
Power Supply Sequencing
It may be advisable to have the VDD turn on prior to having logic
levels on the inputs. The SMP04 has been designed to be resis-
tant to latch-up, but standard precautions should still be taken.
OUTPUT BUFFERS (Pins 1, 2, 14 and 15)
The buffer offset specification is –10 mV; this is less than 1/2 LSB
of an 8-bit DAC with 10 V full scale. Change in offset over the
output range is typically 3 mV. The hold step is the magnitude
of the voltage step caused when switching from sample-to-hold
mode. This error is sometimes referred to as the pedestal
error or sample-to-hold offset, and is about 2 mV with little
variation. The droop rate of a held channel is 2 mV/ms typical
and –25 mV/ ms maximum.
The buffers are designed primarily to drive loads connected to
ground. The outputs can source more than 1.2 mA each, over
the full voltage range and maintain specified accuracy. In split
supply operation, symmetrical output swings can be obtained by
restricting the output range to 2 V from either supply.
On-chip SMP04 buffers eliminate potential stability problems
associated with external buffers; outputs are stable with capaci-
tive loads up to 500 pF. However, since the SMP04’s buffer
outputs are not short-circuit protected, care should be taken to
avoid shorting any output to the supplies or ground.
SIGNAL INPUT (Pins 3, 5, 11 and 12)
The signal inputs should be driven from a low impedance
voltage source such as the output of an op amp. The op amp
should have a high slew rate and fast settling time if the SMP04’s
fast acquisition time characteristics are to be maintained. As
with all CMOS devices, all input voltages should be kept within
range of the supply rails (VSS £ VIN £ VDD) to avoid the possibil-
ity of setting up a latch-up condition.
The internal hold capacitance is typically 60 pF and the internal
switch ON resistance is 2 kW.
If single supply operation is desired, op amps such as the OP183
or AD820, that have input and output voltage compliances
including ground, can be used to drive the inputs. Split sup-
plies, such as –7.5 V, can be used with the SMP04 and the
above mentioned op amps.
APPLICATION TIPS
All unused digital inputs should be connected to logic LOW
and the analog inputs connected to analog ground. For connec-
tors or driven analog inputs that may become temporarily dis-
connected, a resistor to VSS or analog ground should be used
with a value ranging from 0.2 MW to 1 MW.
Do not apply signals to the SMP04 with power off unless the
input current’s value is limited to less than 10 mA.
Track-and-holds are sensitive to layout and physical connections.
For the best performance, the SMP04 should not be socketed.
SMP04
Optimizing Dynamic Performance of the SMP04
Various operating parameters such as input voltage amplitude,
sampling pulsewidth and, as mentioned before, supply bypass-
ing and grounding all have an effect on the signal-to-noise ratio.
Table I shows the SNR versus input level for the SMP04.
Distortion of the SMP04 is reduced by increasing the supply
voltage. This has the effect of increasing the positive slew rate.
Table II shows data taken at 12.3 kHz sample rate and 2 kHz
input frequency. Total harmonic distortion is dominated by the
second and third harmonics.
FREQUENCY DOMAIN PERFORMANCE
The SMP04 has been characterized in the frequency domain for
those applications that require capture of dynamic signals. See
Figure 16a for typical 86.1 kHz sample rate and an 8 kHz input
signal. Typically, the SMP04 can sample at rates up to 85 kHz.
In addition to the maximum sample rate, a minimum sample
pulsewidth will also be acceptable for a given design. Our testing
shows a drop in performance as the sample pulsewidth becomes
less than 4 ms.
Figure 16.Spectral Response at a Sampling Frequency of
86 kHz. Photo (a) Shows a 20 kHz Carrier Frequency and
Photo (b) Shows an 8 kHz Frequency.
Table III shows the effect of sampling pulsewidth on the SNR of
the SMP04. The recommended operating pulsewidth should be
a minimum of 5 ms to achieve a good balance between acqui-
sition time and SNR for the 1.4 V p-p signal shown. For larger
swings the pulsewidth will need to be larger to account for
the time required for the signal to slew the additional voltage.
This could be used as a method of measuring acquisition
time indirectly.
Table I.SNR vs. VIN
Conditions: VS = –6 V, fS = 14.4 kHz,
fIN = 1.8 kHz, tPW = 10 ms.
Table II.SNR vs. Supply Voltage
Supply
Voltage
(V)
Table III.SNR vs. Sample Pulsewidth
Conditions: VS = –6 V, VIN = 1.4 V p-p,
fS = 14.4 kHz, fIN = 1.8 kHz.

Partno	Mfg	Dc	Qty	Available	Descript
SMP04EP	PMI	N/a	9	avai	CMOS Quad Sample-and-Hold Amplifier
SMP04EQ	AD	N/a	15	avai	CMOS Quad Sample-and-Hold Amplifier
SMP04ES	AD	N/a	39	avai	CMOS Quad Sample-and-Hold Amplifier
SMP04ES	ADI	N/a	67	avai	CMOS Quad Sample-and-Hold Amplifier