SMJ320VC33HFGM150 ,Digital Signal ProcessorFeatures • Conditional Calls and Returns• Interlocked Instructions for Multiprocessing1• High-Perfo ..
SMJ34020AGBM32 , GRAPHICS SYSTEM PROCESSORSMJ34020AGRAPHICSSYSTEMPROCESSORSGUS011D -- APRIL 1991 -- REVISED SEPTEMBER 2004D ClassBHigh-Reliab ..
SMJ34020AGBM40 , GRAPHICS SYSTEM PROCESSORSMJ34020AGRAPHICSSYSTEMPROCESSORSGUS011D -- APRIL 1991 -- REVISED SEPTEMBER 2004D ClassBHigh-Reliab ..
SMJ34020AHTM40 , GRAPHICS SYSTEM PROCESSORSMJ34020AGRAPHICSSYSTEMPROCESSORSGUS011D -- APRIL 1991 -- REVISED SEPTEMBER 2004D ClassBHigh-Reliab ..
SMK0460F , SWITCHING REGULATOR APPLICATIONS
SMK0760F , SWITCHING REGULATOR APPLICATIONS
SN74ALS04BDBR ,Hex Invertersmaximum ratings” may cause permanent damage to the device. These are stress ratings only, andfuncti ..
SN74ALS04BDR ,Hex Inverterselectrical characteristics over recommended operating free-air temperature range (unlessotherwise n ..
SN74ALS04BDRG4 ,Hex Inverters 14-SOIC 0 to 70 SDAS063B − APRIL 1982 − REVISED DECEMBER 1994SN ..
SN74ALS04BN ,Hex Invertersmaximum ratings” may cause permanent damage to the device. These are stress ratings only, andfuncti ..
SN74ALS04BNSR ,Hex Invertersmaximum ratings over operating free-air temperature range (unless otherwise noted)Supply voltage, V ..
SN74ALS05A ,Hex Inverters With Open-Collector Outputsmaximum ratings” may cause permanent damage to the device. These are stress ratings only, andfuncti ..
SMJ320VC33HFGM150
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SM320VC33, SMJ320VC33SGUS034F –FEBRUARY 2001–REVISED JUNE 2015
SMx320VC33 Digital Signal Processor Features • Conditional Calls and Returns Interlocked Instructions for Multiprocessing High-Performance Floating-Point Digital Signal
SupportProcessor (DSP) Bus-Control Registers Configure Strobe-Control– SMx320VC33-150
Wait-State Generation– 13-ns Instruction Cycle Time • 1.8-V (Core) and 3.3-V (I/O) Supply Voltages– 150 Million Floating-Point Operations per
Second (MFLOPS)
2 Description– 75 Million Instructions per Second (MIPS) The SMx320VC33 DSPisa 32-bit, floating-point• 34K× 32-Bit (1.1-Mbit) On-Chip Wordsof Dual- processor manufacturedin 0.18-μm four-level-metalAccess Static Random-Access Memory (SRAM) CMOS (TImeline) technology. The SMx320VC33is
Configuredin2× 16K plus2× 1K Blocksto partof the SM320C3x™ generationof DSPs from
Texas Instruments.Improve Internal Performance x5 Phase-Locked Loop (PLL) Clock Generator The SM320C3x internal busing and special digital-
signal-processing instruction set have the speed and• Very-Low Power: <200 mWat 150 MFLOPS
flexibility to execute up to 150 MFLOPS. The• 32-Bit High-Performance CPU SMx320VC33 optimizes speed by implementing• 16-/32-Bit Integer and 32-/40-Bit Floating-Point functions in hardware that other processorsOperations implement through software or microcode. This
hardware-intensive approach provides performance• Four Internally Decoded Page Strobesto Simplify
previously unavailableona single chip.Interfaceto I/O and Memory Devices Boot-Program Loader The SMx320VC33 can perform parallel multiply and
ALU operations on integeror floating-point dataina• EDGEMODE Selectable External Interrupts single cycle. Each processor also possessesa• 32-Bit Instruction Word, 24-Bit Addresses general-purpose register file,a program cache,• Eight Extended-Precision Registers dedicated ARAUs, internal dual-access memories,
one DMA channel supporting concurrent I/O, anda• Fabricated Using the 0.18-μm (leff– Effective Gate
short machine-cycle time. These features resultinLength) TImeline™ Technologyby Texas high performance and easeof use. General-purposeInstruments applications are greatly enhanced by the large• On-Chip Scan-Based Emulation Logic, IEEE Std address space, multiprocessor interface, internally1149.1 (JTAG) and externally generated wait states, one external On-Chip Memory-Mapped Peripherals: interface port, two timers, one serial port, and
multiple-interrupt structure.– One Serial Port Two 32-Bit Timers The SM320C3x supportsa wide varietyof system
applications from host processor to dedicated– Direct Memory Access (DMA) Coprocessor for coprocessor. High-level-language supportis easilyConcurrent I/O and CPU Operation implemented througha register-based architecture,• 164-Pin Low-Profile Quad Flatpack (HFG Suffix) large address space, powerful addressing modes, Ceramic Ball Grid Array flexible instruction set, and well-supported floating-
point arithmetic. With Eight Auxiliary
Device Information(1) Arithmetic
