SG3524P013TR Fast Delivery |IC PHOENIX CO.,LIMITED

SG3524P013TR ,REGULATING PULSE WIDTH MODULATORSAPPLICATIONSLOW STANDBY CURRENT 8mA TYPICALOPERATION UP TO 300KHz1% MAXIMUM TEMPERATURE VARIATIONOF ..
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SG3524P013TR
REGULATING PULSE WIDTH MODULATORS
SG3524
REGULATING PULSE WIDTH MODULATORS
COMPLETE PWM POWER CONTROL CIR-
CUITRY
UNCOMMITTED OUTPUTS FOR SINGLE-
ENDED OR PUSH PULL APPLICATIONS
LOW STANDBY CURRENT 8mA TYPICAL
OPERATION UP TO 300KHz
1% MAXIMUM TEMPERATURE VARIATION
OF REFERENCE VOLTAGE
DESCRIPTION
The SG3524 incorporates on a single monolithic
chip all the function required for the construction
of regulating power suppies inverters or switching
regulators. They can also be used as the control
element for high power-output applications. The
SG3524 family was designed for switching regu-
lators of either polarity, transformer-coupled dc-
to-dc converters, transformerless voltage dou-
blers and polarity converter applications
employing fixed-frequency, pulse-width modula-
tion techniques. The dual alternating outputs al-
lows either single-ended or push-pull applications.
Each device includes an on-ship reference, error
amplifier, programmable oscillator, pulse-steering
flip flop, two uncommitted output transistors, a
high-gain comparator, and current-limiting and
shut-down circuitry.
BLOCK DIAGRAM
ABSOLUTE MAXIMUM RATINGS
THERMAL DATA
(*) Thermal resistance junction-alumina with the device soldered on the middle of an alumina supporting substrate measuring 15 x 20mm;
0.65mm thickness with infinite heatsink.
PIN CONNECTION (Top view)
SG3524
2/9
ELECTRICAL CHARACTERISTICS (unless otherwise stated, these specifications apply for Tj = 0 to
70°C, VIN = 20V, and f = 20KHz).
(*) Excluding oscillator charging current, error and current limit dividers, and with outputs open.
SG3524
3/9
Figure 1: Open-loop Voltage Amplification of
Error Amplifier vs. Frequency
Figure 2: Oscillator Frequency vs. Timing
Components.
Figure 3: Output Dead Time vs. Timing
Capacitance Value.
Figure 4: Output Saturation Voltage vs. load
Current.
Figure 5: Open Loop Test Circuit.
SG3524
4/9
PRINCIPLES OF OPERATION
The SG3524 is a fixed frequency pulse-with-
modulation voltage regulator control circuit. The
regulator operates at a frequency that is pro-
grammed by one timing resistor (RT) and one tim-
ing capacitor (CT). RT established a constant
charging current for CT. This results in a linear
voltage ramp at CT, which is fed to the compara-
tor providing linear control of the output pulse
width by the error amplifier. the SG3524 contains,
an on-board 5V regulator that serves as a refer-
ence as well as powering the SG3524’s internal
control circuitry and is also useful in supplying ex-
ternal support functions. This reference voltage is
lowered externally by a resistor divider to provide reference within the common mode range the
error amplifier or an external reference may be
used. The power supply output is sensed by a
second resistor divider network to generale a
feedback signal to error amplifier. The amplifier
output voltage is then compared to the linear volt-
age ramp at CT. The resulting modulated pulse
out of the high-gain comparator is then steered to
the appropriate output pass transistors (QA or QB)
by the pulse-steering flip-flop, which is synchro-
nously toggled by the oscillator output. The oscil-
lator output pulse also serves as a blanking pulse
to assure both output are never on simultane-
ously during the transition times. The width of the
blanking pulse is controlled by the value of CT.
The outputs may be applied in a push-pull con-
figuration in which their frequency is half that of
the base oscillator, or paralleled for single-ended
applications in which the frequency is equal to
that of the oscillator. The output of the error am-
plifier shares a common input to the comparator
with the current limiting at shutdown circuitry and
can be overridden by signals from either of these
inputs. This common point is also available exter-
nally and may be employed to control the gain of,
or to compensate, the error amplifier, or to pro-
vide additional control to the regulator.
RECOMMENDED OPERATING CONDITIONS
TYPICAL APPLICATIONS DATA
OSCILLATOR
The oscillator controls the frequency of the
SG3524 and is programmed by RT and CT ac-
cording to the approximate formula:
f = 1.18
RT CT
where:
RT is in KΩ
CT is in μF
f is in KHz
Pratical values of CT fall between 0.001 and
0.1μF. Pratical values of RT fall between 1.8 and
100KΩ. This results in a frequency range typically
from 120Hz to to 500KHz.
BLANKING
The output pulse of oscillator is used as a blank-
ing pulse at the output. This pulse width is con-
trolled by the value of CT.If small values of CT are
required for frequency control, the oscillator out-
put pulse width may still be increased by applying
a shunt capacitance of up to 100pF from pin 3 to
ground. If still greater dead-time is required, it
should be accomplished by limiting the maximum
duty cycle by clamping the output of the error am-
plifier. This can easily be done with the circuit be-
low:
SYNCRONOUS OPERATION
When an external clock is desired, a clock pulse
of approximately 3V can be applied directly to the
oscillator output terminal. The impedance to
ground at this point is approximately 2KΩ. In this
configuration RT CT must be selected for a clock
period slightly greater than that the external clock.
If two more SG2524 regulators are to be operated
synchronously, all oscillator output terminals
should be tied together, all CT terminals con-
nected to a single timing capacitor, and timing re-
sistor connected to a single RT terminal. The
other RT terminals can be left open or shorted to
VREF. Minimum lead lengths should be used be-
tween the CT terminals.
Figure 6.
SG3524
5/9
Figure 7: Flyback Converter Circuit.
Figure 8: PUSH-PULL Transformer-coupled circuit.
SG3524
6/9

Partno	Mfg	Dc	Qty	Available	Descript
SG3524P013TR	ST	N/a	2500	avai	REGULATING PULSE WIDTH MODULATORS