SERCON410B Fast Delivery |IC PHOENIX CO.,LIMITED

SERCON410B ,SERCOS INTERFACE CONTROLLERSERCON410BDATASHEETUSE IN LIFE SUPPORT DEVICES OR SYSTEMS MUST BE EXPRESSLY AUTHORIZED.SGS-THOMSON ..
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SERCON410B
SERCOS INTERFACE CONTROLLER
SERCON410B
DATASHEET
USEIN LIFE SUPPORT DEVICES OR SYSTEMSMUST BE EXPRESSLYAUTHORIZED.
SGS-THOMSON PRODUCTS ARE NOT AUTHORIZED FOR USEAS CRITICAL COMPONENTSIN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVALOF SGS-THOMSON Microelectronics. used herein: Life support devicesor systems are those which(a) are
intendedfor surgical implantintothe body,or (b)support sustain life, and whose failureto perform, when prop-
erly usedin accordance with instructionsfor use pro-
vided with the product, canbe reasonably expectedtoA critical componentis any componentofalife support
deviceor system whose failureto perform can reason-
ablybe expectedto causethe failureofthelife support
deviceor system, orto affectits safetyor effectiveness.
SERCON410B DATASHEET
INDEX
Page
Number
SERCON410B.. ...... ..... .... .......... ......... 1 GENERAL DESCRIPTION ...... .. .... .. ..... .... ...... .. 5 PIN DESCRIPTION... ..... ............ .. .. ......... ... .. .. 6 ELECTRICAL CHARACTERISTICS... .. .. ....... .. .......... .. ... 9
3.1 ABSOLUTEMAXIMUM RATINGS............................. 9
3.2 RECOMMENDED OPERATING........................ ...... 9
3.3 DC ELECTRICAL CHARACTERISTICS.......................... 9
3.4 AC ELECTRICAL CHARACTERISTICS.......................... 11
3.4.1 Clock Input MCLK................................ 11
3.4.2 Clock Input SCLK......... ....... ................. 11
3.4.3 Serial Clock.................................... 12
3.4.4 AddressLatch........................... ..... .. 12
3.4.5 ReadAccessof Control Registers........................ 13
3.4.6 ReadAccessof Dual Port RAM.................. ..... .. 14
3.4.7 Write Accessto Control Registers..... ................... 15
3.4.8 Write Accessto Dual Port RAM.......................... 16 CONTROL REGISTERS AND RAM DATA STRUCTURES.......... .... ...... 17
4.1 CONTROL REGISTER ADDRESSES........................... 17
4.2 DATA STRUCTURES WITHIN THE RAM......................... 23
4.2.1 Telegram Headers................................ 23
4.2.2 Data Containers..................... ............ 25
4.2.3 EndMarker.................................... 26
4.2.4 Service Containers................................ 26 PACKAGE MECHANICAL DATA ............. .. .. .. ....... ... .. .. 29 ADDITIONAL SUPPORTAND TOOLS ... .. .. .. ... .. .. ....... ... .... 29
6.1 SERCOS INTERFACE SPECIFICATION......................... 29
6.2 SOFTWARE AND BOARDS FOR THE SERCON410B.................. 29
NOTES:
SERCON410B
SERCON410B
PRELIMINARY DATA
SERCOS INTERFACE CONTROLLER
(Ordering Number: SERGBQA)
PQFP100
Single-chipcontrollerfor SERCOS interface
Real time communicationfor industrial control
systems
8/16-bitbus interface,Intel and Motorola con-
trol signals
Dual port RAM with 1024 words* 16-bit
Data communications via optical fiber rings, RS
485 rings and RS 485 busses
Maximum transmission rateof4 Mbaud within-
ternal clock recovery
Maximum transmission rateof10 Mbaud with
external clock recovery
Internal repeaterfor ring connections
Full duplex operation
Modulationof powerof optical transmitter diode
Automatic transmissionof synchronous and
data telegramsin the communication cycle
Flexible RAM configuration, communication
data storedin RAM (singleor double buffer)or
transfer via DMA
Synchronizationby external signal
Timing control signals
Automatic service channel transmission
100-pin plastic flat-packcasing
Figure1. SERCON410B Block Diagram
SERCON410B
Figure2. SERCON410B Pin Configuration
SERCON410B
Figure3. SERCOS Interface with Ring Connection
Figure4. SERCON410B with RS-485 bus Connection
SERCON410B
GENERAL DESCRIPTIONThe SERCOS interface controller SERCON410Ban integrated circuit forSERCOS interfacecom-
munication systems. The SERCOS interfaceisa
digital interface for communication between sys-
tems which haveto exchange information cycli-
callyat short, fixed intervals (65 μsto65 ms).Itis
appropriatefor the synchronous operationof dis-
tributed controlor test equipment (e.g. connection
between drives and numeric control). SERCOS interface communication system con-
sistsof one master and several slaves (Fig. 3).
These units are connectedbya fiber optical ring.
This ring starts and endsat the master. The slaves
regenerate and repeat their received dataor send
their own telegrams.By this method the telegrams
sentby the master are receivedbyall slaveswhile
the master receives data telegrams from the
slaves. The optical fiber assuresa reliable high-
speed data transmission with excellent noise im-
munity.
The SERCOS interface controller containsall the
hardware-related functionsof the SERCOS inter-
face and considerably reduces the hardware
costs and the computing time requirementsof the
microprocessor.Itis the direct link between the
electro-optical receiver and transmitter and the mi-
croprocessor that executes the control algorithms.
The SERCON410B canbe used bothfor SERCOS
interface mastersand slaves.
The circuitcontains the following functions (Fig.1): Interfaceto the microprocessor witha data
bus widthof8or 16 bits and with control lines
accordingto Intelor Motorola standards.A serial interface for makinga direct connec-
tion with the optical receiver and transmitterof
the fiber optic ringor with driversto an electric
ringor bus. Data and clock regeneration, the
repeater for ring topologies and the serial
transmitter and receiver are integrated. The
signals are monitored and test signals gener-
ated. The serial interface operates up to
4Mbaud without external circuitry and upto10
Mbaud with external clock regeneration.A dual port RAM (1024*16 bit)for control and
communication data. The organizationof the
memoryis flexible. Telegram processing for automatic transmis-
sion and monitoringof synchronous and data
telegrams. Only transmission data whichis in-
tended for the particular interface useris proc-
essed. The transmitted datais either storedin
the internal RAM (singleor double buffer)or
transferred via direct memory access (DMA).
The transmissionof service channel informa-
tion over several communication cyclesis exe-
cuted automatically. additionto the SERCOS interface the SER-
CON410B can also be used for other real-time
communications tasks.Asan alternativeto thefi-
beroptical ring also bus topologies with RS-485
signals are supported (Fig.4). The SERCON410B therefore suitable fora wide rangeof applica-
tions.
SERCON410B
PIN DESCRIPTIONSignal(s) Pin(s) IO Function
D15-0
77-80,
82-85,
87-90,
I/O
Data bus:for 8-bit-wide bus interfaces, datais writtento and readvia D7-0,
for 16-bit-wide bus interfacesvia D15-0. When ADMUXis1,the address
whichis storedinthe address latch with ALEL and ALEH isinputvia D15-0.
A15-0
56-59,
61-64,
66-69,
I/O
Address bus: when ADMUXis0 thepins are inputs, when ADMUXis1, they
are outputsforthe address stored with ALEL (A7-0) and ALEH (A15-8).In
the 8-bit bus mode,A0 distinguishes which byteis transmittedvia
D7-0 (dependson BYTEDIR).Inthe 16-bit bus mode, datais tansferredvia
D7-0 onlywhenA0 is0. A10-1 selectsthe wordsofthe internal RAM; A6-
1the control registers.
ALEL, ALEH 54,53 I
Address latch enable, low and high, active high: theyare only used when
ADMUXis1. When ALEL/ALEHis1, the signalsgo from the data busto
the address bus, when ALEL/ALEH=0, they store the address. When
ADMUXis0, ALEL/ALEH havetobe connectedto VDD.
RDN 51 I
Read: forthe Intel bus interface, datais read when RDNis0. Forthe
Motorola bus interface, datais reador writtento when RDNis0
(BUSMODE1=0)or RDNis1 (BUSMODE1=1).
WRN 52 I
Write:forthe Intel bus interface, datais writtento whenWRNis0. For the
Motorola bus interface, WRN selects read (WRN=1) and write (WRN=0)
operationsofthe data bus.
BHEN 75 I Byte high enable, active low:inthe 16-bit bus mode, datais transferredvia
D15-8 when BHENis0.
MCSN0,
MCSN1 46,47 I Memory chipselect, active low:to accessthe internal RAM MCSN0 and
MCSN1 mustbe0.
PCSN0,
PCS1 48,49 I Periphery chip select, active low (PCSN0) and active high (PCSN1):to
accessthe control registers PCSN0 must equal 0and PCS1 must equal1.
BUSYN 45 O
RAM busy, active low: becomes activeifan accesstoan address ofthe
dual port RAMis performed simultaneouslytoan accesstothe same
memory locationbythe internal telegram processing.
DMAREQR 38 O
DMA request receive, active high: becomes active ifdata fromthe receive
FIFO canbe read.Atthe beginningofthe read operationofthe last wordof
the receive FIFO, DMAREQR becomes inactive.
DMAACKRN 40 I DMA acknowledge receive, active low: when DMAACKRNis0,the receive
FIFOis read, independentofthe levelson A6-1 andthe chip select signals.
DMAREQT 39 O
DMA request transmit, active high: becomes active when datacanbe
writtento the transmit FIFO. DMAREQT becomesinactive againatthe
beginningofthe last write accesstothe transmit FIFO.
DMAREQTN 41 I
DMA acknowledge transmit, active low: when DMAACKTNis0, the
transmit FIFOis writtento when thereisa bus write access independentof
the levelson A6-1 andthe chip select signals.
ADMUX 96 I Address data bus: when ADMUXis0 A15-0arethe address inputs, when
ADMUXis1 A15-0arethe outputsofthe address latch.
BUSMODE0,
BUSMODE1 97,98 I
Bus mode: BUSMODE0=0 turnsonthe Intelbus interface (RDN= read,
WRN= write), BUSMODE0= 1selectsthe Motorola interface (RDN= data
strobe,WRN= read/write). BUSMODE1 selectsthe 0-activedata strobe
(BUSMODE1= 0)orthe 1-active data strobe(BUSMODE1=1).
BUSWIDTH 99 I Bus width: selectsthe 8-bit-(0)or the16-bit-wide interface(1).
Table1. SERCON410B I/O Port Function Summary
SERCON410B
PIN DESCRIPTION (Continued)
Signal(s) Pin(s) IO Function
BYTEDIR 100 I
Byte address sequence: when BYTEDIRis0,A0=0 addressesthe lower bitsof aword (low byte first), when BYTEDIRis1,the upper8 bitsofa
word areaddressed (high byte first).
INT0, INT1 44,43 O Interrupts, active lowor active high. Interrupt sources and signalpolarity
are programmable.
SREGEN 28 I
Internal regeneration. When SREGENis 0,clock and data regeneration
are turnedoff. RxC and TxCare clock inputs. WhenSREGENis1, clock
and dataregeneration are turnedon. RxC and TxC outputthe internally
generated clocks.
SBAUD 29 I
Baud rate. When regenerationis turnedon, SBAUD selectsthe baud rate
(fSCLK/16 when SBAUDis0, fSCLK/32 when SBAUDis1). Canbe
overwrittenbythe microprocessor.
RxD 14 I Receive data forthe serial interface.
RxC
I/O
Receive clockforthe serial interface. When regenerationis turnedoff
(SREGEN=0), clock inputfor the serial receiver and transmitter(only
when repeateris turned on); when regenerationis turnedon (SREGEN=1)
outputofthe internally generated receive clock. The maximum frequency10 MHz.
RECACTN 26 O Receive active, active low. Indicates thatthe serial receiveris receivinga
telegram.
TxD1 16 O Transmit data. Thepin canbe switchedtoa high impedance state.
TxD6-2 22,21,2
18,17
Transmit dataor output port. The pins either outputthe serial dataor can usedas parallel output ports. When they output transmit data, eachpin
canbe switchedtoa high impedance state individually.
TxDNRZ 24 O NRZ-coded transmit data.
TxC
I/O
Transmit clock forthe serial interface. When regenerationis turnedoff
(SREGEN=0) andthe repeateris turnedoff,itisthe clock inputforthe
serial transmitter; when regenerationis turnedon (SREGEN=1)itisthe
outputforthe internally generated transmit clock. The maximum frequency10 MHz.
IDLE 25 O Transmitter active, active low. When transmitting own data IDLEis0.
TM0, TM1 30,31
Turnon test generator: TM0=0 switches TxD1-6to continuous signal light,
TM1=0 switch-overto zerobit stream. The processor can overwritethe
levelof TM1-0.
L_ERRN 32
Line error, active low: goes low when signal distortionistoo highor when
the receive signalis missing. The operating modeis programmed bythe
processor.
CYC_CLK 34 I SERCOS interface cycle clock: CYC_CLK synchronizesthe
communication cycles. The polarityis programmable.
CON_CLK 35 O Control clock: becomes active withina communication cycle. Time,
polarity and width are programmable.
DIV_CLK 36 O
Divided control clock: becomes active several times withina ommunication
cycle. Numberof pulses, start time, repetition rate and polarity are
programmable,the pulse width is1μs.
SCLK 2 I Serial clockfor clock regeneration:the frequencyis16or32 timesthe
baud rate,the maximum frequencyis64 MHz.
Table1. SERCON410B I/O Port Function Summary (Continued)
SERCON410B
Signal(s) Pin(s) IO Function
SCLKO2 6 O Clock output: outputsthe SCLK clock dividedby2.
SCLKO4 5 O Clock output: outputsthe SCLK clock dividedby4.
MCLK 4 I Master clockfor telegram processing and timing control, frequency12to20
MHz.
RSTN 10 I Reset, active low. Mustbe zeroforat least50ns after power on.
TEST 7 I Test, active high. Hastobe tiedto VSS.
OUTZ 11 I
Puts outputs into high impedance state, active high: OUTZis1 putsall pins
intoa high impedance state. The clocks are turnedoff andthe circuitis
reset. Forthe in-circuit test andfor turningonthe powerdown mode.
NDTRO 9 O
NAND tree output. Forthe testat the semiconductor manufacturers andfor
the connection test after boardproduction. NDTRO isnot settoa high
impedance state.
VSS
3,15,23,
33,42,
50,60,
70,81,
Ground pins.
VDD
1,8,19,
27,37,
55,65,
76,86
Power supply+5 V± 5%.
Table1. SERCON410B I/O Port Function Summary (Continued)
PIN DESCRIPTION (Continued)
SERCON410B
ELECTRICALCHARACTERISTICS3.1 ABSOLUTE MAXIMUM RATINGS
Symbol Parameter Value Unit
VDD Supply Voltage -0.3to7.0 V Input Voltage VSS-0.3to VDD+0.3 V Output Voltage VSS-0.3to VDD+0.3 V
TSTG Storage Temperature -55to +150 °C
3.2 RECOMMENDED OPERATING CONDITIONS
Symbol Parameter
Value
Unit
Min. Max. Operating Temperature -40 85 °C
VDD Operating SupplyVoltage 4.75 5.25 V
fSCLK Clock Frequency SCLK 64 MHz
fMCLK Clock Frequency MCLK 20 MHz
fTxC,fRxC Clock Frequency TxC, RxC 10 MHz
Symbol Parameter Test Conditions
Value
Unit
Min. Typ. Max.
VIL Input Low Level Voltage 0.8 V
VIH Input HighLevel Voltage 2.4 V
VT+
Schmitt trig. +ve threshold All pinsexcept
D15-0, A15-0,
ALEL, ALEH,
RDN, WRN,
BHEN, MCSN0-1,
PCSN0, PCS1,
DMAACKTN,
DMAACKRN
2.0 2.4 V
VT- Schmitt trig. +ve threshold 0.6 0.8 V
(VDD =5V± 5% TA= -40°Cto +85°C, unless otherwise specified)
3.3 DC ELECTRICAL CHARACTERISTICS
SERCON410B
Symbol Parameter Test Conditions
Value
Unit
Min. Typ. Max.
IIL Low Level Input Current
(Pull-up resistor) VI= VSS -450 -50 -30 μA
IIH High Level Input Current VI= VDD -10 <1 10 μA
VOL Low levelOutput Voltage,
allO- and I/O-pins except TXD6-1 IOI=-4 mA 0.4 V
VOH High level output voltage,
allO- and I/O-pins except TXD6-1 IOH=+4 mA 2.4 V
VOL High level outputvoltage,
allO- and I/O-pins except TXD6-1 IOI=-8 mA 0.4 V
VOH High level output voltage,
pins TXD6-1 IOH=+8 mA VDD-0.5
IOZ Tri-state output leakage VO =0Vor VDD -10 <1 +10 μA
IKLU I/O latch-up current VVDD 200mA mA
VESD Electrostatic protection C=100 pF,R=1.5k 2000 V
CPIN Pin capacitance 10 pF ELECTRICALCHARACTERISTICS (Continued)
SERCON410B
Figure5. Timingof Clock MCLK and Related Outputs
(Cload =50 pF, VDD =5V± 5%TA= -40°Cto +85 °C)
3.4 AC ELECTRICAL CHARACTERISTICS
3.4.1 Clock Input MCLK
Symbol Parameter
Value
Unit
Min. Type Max.
fMCLK Clock Frequency MCLK 12 20 MHz
tMCLK0 MCLK Low 20 ns
tMCLK1 MCLK High 20 ns
tMCLD Output Delay Rising Edge MCLKto
DMAREQR/T, CON_CLK, DIV_CLK 30 ns
Figure6. Timingof Clock SCLK
3.4.2 Clock Input SCLK
Symbol Parameter
Value
Unit
Min. Type Max.
fSCLK Clock Frequency SCLK 64 MHz
tSCLK0 SCLK Low 6.5 ns
tSCLK1 SCLK High 6.5 ns
SERCON410B
Figure7. Timingof Serial Clock Inputs RxC and TxC and Related Signals ELECTRICALCHARACTERISTICS (Continued)
3.4.3 Serial Clock
Symbol Parameter
Value
Unit
Min. Type Max.
fRTXC Clock Frequency RxC, TxC 10 MHz
tRTXC0 RxC, TxC Low 40 ns
tRTXX1 RxC, TxC High 40 ns
tRTOUT Output Delay RxC, TxCto TxD6-1,
TxDNRZ, IDLE, RECACTN 45 ns
tRXDSU Setup RxDto Falling Edgeof RxC 15 ns
(SREGEN=0, external clock regeneration, RxC and TxC are inputs)
Figure8. Timingof Serial Clock Inputs RxC and TxC and Related Signals
3.4.4 Address Latch
Symbol Parameter
Value
Unit
Min. Type Max.
tALEW Pulse Width ALEL, ALEH 25 ns
tALESU Setup Time D15-0 ToFalling Edge ALEH,
ALEL 10 ns
tALEHD Hold Time Falling Edge ALEH, ALELto D15-0 5 ns
SERCON410B
Figure9. Read Accessof Control Registers ELECTRICALCHARACTERISTICS (Continued)
3.4.5 ReadAccessof Control Registers
Symbol Parameter
Value
Unit
Min. Type Max.
tASU
Setup time A6-0, BHEN, PCSN0, PCS1,
DMAACKNR, WRN (only Motorola mode)to
falling edge RDN (Intelor Motorola mode
with low active strobe)or rising edge RDN
(Motorola mode with high active strobe)
0ns
tAHD
Hold time A10-0, BHEN, MCSN0-1, WRN
(only Motorola mode)to rising edge RDN
(Intel Motorola mode with low active strobe) falling edgeRDN (Motorola mode with high
active strobe)
0ns
tPAD
Access time A6-0, BHEN, PCSN0, PCS1,
DMAACKNR, WRN (only Motorola mode)to
D15-0 valid ns
tPRDD Access time RDNto D15-0 valid 40 ns
tRDZ Delay RDNto D15-0 high-Z 15 ns
tPRQ Delay RDNto DMAREQR low 30 ns
SERCON410B

Partno	Mfg	Dc	Qty	Available	Descript
SERCON410B	ST	N/a	23	avai	SERCOS INTERFACE CONTROLLER