SDA9254-2 ,Triple TV SAMFunctional DescriptionGeneralThe SDA 9254-2 is a combination of the TV-SAM SDA 9253 and an adaptive ..
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SDA9254-2
Triple TV SAM
SIEMENS
2.6 MBit Dynamic Sequential Access Memory
for Television Applications (TV-SAM) with
On-chip Noise Reduction Filter
Preliminary Data
Features
Stores a complete video field (4:1 :1)
On chip adaptive recursive noise reduction filter (4:1:1)
4 noise reduction classes selectable
Special noise reduction mode for 4:2:2 applications
212 M 64 M 16 M 12-bit organization
Triple port architecture
One 16 M 12-bit input shift register
Two 16 x 12-bit output shift registers
Shift registers independently and simultaneously
accessible (one output shift register is used internally for
noise reduction filtering)
Continuous data flow even at maximum speed
40-MHz shift rate - 0.96-Gbit/s total data rate
All inputs and outputs TTL-compatible
Tristate outputs
Random access of groups of 16 x 12 bits for a wide range
of applications
Refresh-free operation possible
5 V i 10 % power supply
0 ... 70 °C operating temperature range
Low power dissipation: 700 mW active, 28 mW standby
Suitable for all common TV standards
Allows flicker and noise reduction simultaneously
with only one field memory
Applications: TV, VCR, image processing,
video printers, data compressors, delay lines,
time base correctors, HDTV
SDA 9254-2
CMOS IC
P-MQFP-64-1
Type Ordering Code
Package
SDA 9254-2 on request
P-MQFP-64-1
Semiconductor Group 1
SIEMENS SDA 9254-2
Functional Description
General
The SDA 9254-2 is a combination of the TV-SAM SDA 9253 and an adaptive recursive filter to
achieve a reduction of noise for video signals. To get a closed loop one of the two output ports of
the triple port memory is connected internally to the noise reduction filter. External access to this
port is not possible. The characteristic of the noise reduction filter is adjustable via three pins
(CLASS, CLASS1, CLASSO).
SDCO...11 o-Ir' T PortC
BLN 0—, Noise .
Reduction Field
NR422 0—) Filter Memory
CLASS 0+» " PortB PortA +> SQAO...11
3 12 12 UEB10379
Figure1
Block Diagram
The memory capacity of the SDA 9254-2 enables a field based filtering of 4:1 :1 video signals (pin
NR422 = ly). 4:2:2 applications are supported by a special noise reduction mode (pin NR422 = 'I').
In this mode filtering is applied only to the luminance signal, the chrominance signals are delayed
by an internal delay line but remain unfiltered. For the storage of 4 bit planes of the chrominance
signal a SDA 9251-2X is requested additionally.
Semiconductor Group 2 1998-01-16
