SDA9188-3X GEG ,Picture-in-Picture Processor with On-...featureType Ordering Code PackageSDA 9188-3X Q67100-H5142 P-DSO-28-3 (350 mil) (SMD)
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SDA9189XA132 ,Quarter PIP ProcessorICs for Consumer ElectronicsQuarter PIP ProcessorSDA 9189X (A123 / A132)4PIPData Sheet 03.96Edition ..
SDA9189XA132 ,Quarter PIP ProcessorICs for Consumer ElectronicsQuarter PIP ProcessorSDA 9189X (A123 / A132)4PIPData Sheet 03.96Edition ..
SDA9189XA132 ,Quarter PIP Processorapplications, pro-cesses and circuits implemented within com-ponents or assemblies.The information ..
SDA9189XA132 ,Quarter PIP Processorapplications, pro-cesses and circuits implemented within com-ponents or assemblies.The information ..
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SDA9188-3X-SDA9188-3X GEG
Picture-in-Picture Processor with On-...
SUEMENS
Picture-in-Picture Processor with On-Chip PLL SDA 9188-3X
Preliminary Data MOS IC
Features
0 On-chip PLL
0 Full frame display for 50/60 Hz in order to increase the
vertical resolution and to suppress moving artifacts.
Compatibility to the 16:9 display format by means of
independent setting of the vertical and horizontal
decimation factors and the width of the border frame
Decimation of the Y, U, V data for pictures sizes 1/9
and 1/16 with 6 bits width of the input word without
rounding error
P-DSO-28-3
0 Intermediate storage of the inset picture (on-chip-memory)
0 RGB- or Y-, U-, V-signal generation
0 100% pin- and software compatible with SDA 9188X if external PLL is used
0 Increased bandwith of analog outputs due to higher output currents
0 New select function for multi-PIP feature
Type Ordering Code Package
SDA 9188-3X Q67100-H5142 P-DSO-28-3 (350 mil) (SMD)
Functional Description
The SDA 9188-3X Picture-in-Picture (PIP) processor with on-chip PLL combines two asynchronous
picture sources so that a small moving picture (the inset picture) can be superimposed in a moving
picture of normal size (the parent picture).
The components of the video signal of the inset source have to be fed in a digitized form to the
SDA 9188-3X (figure 1). Amplitude resolution of the signal components is 6 bit at a sampling rate
of 13.5 MHz for the luminance signal and 3.375 MHz for the chrominance signals.
Semiconductor Group 1 08.93
SHIEMIENS SDA 9188-3X
The PIP processor SDA 9188-3X handles picture reduction (decimation with horizontally and
vertically acting filters), intermediate data storage in an integrated image memory (169.812 bits) as
well as the output of the decimated picture.
The picture can be set 1/9 or 1/16 of its original size. In order to indicate the border between parent
picture and inset picture the inset picture can be surrounded with a frame: its width is adjustable in
2 stages and its brightness in 16 stages. Different signal sources can be identified by using different
framing colors. The four corners of the parent picture are possible positions for the inset picture. The
inset picture can also be inserted as a still picture, independently of the parent picture.
The output signals of the SDA 9188-3X are analog. Either RGB or Y, U, V signals can be output,
whereby a 6-bit broadband conversion is obtained for all components. Clamping for RGB output
signal is performed in an RGB processor (e.g. TDA 4685).
Only a few additional devices are required for a complete picture-in-picture system. Application
circuits 1a and 1b illustrate the use of the PIP device.
If the CVBS input signal is to be decoded using an analog color decoder for the PIP, the analog/
digital interface for the inset picture (3 AID Converter, SDA 9187-2X) performs the conversion of the
Y, U, V components into digital signals as well as the generation of the inset clocks BLNI and LL3I.
The SDA 9188-3X processes both 50 Hz/625 and 60 Hz/525 line signals. The field frequency can
be 50/60 Hz or 100/120 Hz. For systems with Siemens Dig TV Featurebox a field frequency of 100
Hz or 120 Hz is also possible by doubling the clock frequency LL3P (LL1.5P). Frame mode display
with 50 Hz or 60 Hz can also be set via the PC bus. Adaptation to the number of lines occurs
automatically. If the field frequency in the parent and inset channels are different, artifacts may
result in the picture.
Synchronization with the parent channel is performed via the horizontal and vertical sync signals
HSP/SAND and VSP. The clock fequency is 13.5 MHz (LL3P) without standard conversion and
27 MHz (LL1.5P) with standard conversion (100/120 Hz). The display clock is generated on chip.
Optionally the external clock generator SDA 9086-3 can be used in the same way as with the
SDA 9188X.
The horizontal and vertical sync signals BLNI and VSI plus the LL3l clock (13.5 MHz) are used for
synchronization with the inset source.
The interface between inset and parent channel is done by the on-chip memory. The memory write
access is controlled by the inset clock and the read access is controlled by the parent clock.
The SELECT output signal inserts the inset picture into the parent picture driving an external analog
switch, e.g. the TDA 4685. All operation modes of the SDA 9188-3X can be controlled via the 12C
bus. Nine registers can be used.
Semiconductor Group 2
