SDA3302-5 ,GHz PLL with I2C Bus and Four Chip Ad...Features● 1-chip system for MPU2control (I C bus)● 4 programmable chip addresses● Short pull-in tim ..
SDA3302-5 ,GHz PLL with I2C Bus and Four Chip Ad...block diagram)UHF/VHF The tuner signal is capacitively coupled at the UHF/VHF input andsubsequently ..
SDA3302-5 ,GHz PLL with I2C Bus and Four Chip Ad...Functional DescriptionCombined with a VCO (tuner) the SDA 3302 device, with four hardware-switched ..
SDA3302-5X ,GHz PLL with I2C Bus and Four Chip Ad...Functional DescriptionCombined with a VCO (tuner) the SDA 3302 device, with four hardware-switched ..
SDA3302-5X6 ,GHz PLL with I2C Bus and Four Chip AddressesFeatures● 1-chip system for MPU2control (I C bus)● 4 programmable chip addresses● Short pull-in tim ..
SDA3302-5X6 ,GHz PLL with I2C Bus and Four Chip Addresses 2 SDA 3302 FamilyGHz PLL with I C Busand Four Chip AddressesPreliminary Data Bipolar IC
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SDA3302-5-SDA3302-5X-SDA3302-5X6
GHz PLL with I2C Bus and Four Chip Ad...
SHIEMIIENS
GHz PLL with fc Bus
and Four Chip Addresses
Preliminary Data
SDA 3302 Family
Bipolar IC
Features
0 1-chip system for MPU
control (PC bus)
0 4 programmable chip addresses
0 Short pull-in time for quick channel
switch-over and optimized loop
stability
0 Charge pump output with switch
P-DIP-18-5
P-DSO-20-1
off option
0 Up to 3*) high current band switch
outputs (20 mA)
0 Up to 4*) output ports (5 mA)
*) depending on version
P-DSO-16-1
Type Ordering Code Package
SDA 3302-5 Q67000-H5112 P-DlP-18-5
SDA 3302-5X Q67000-H51 11 P-DSO-20-1 (SMD)
SDA 3302-5X6 Q67000-H5110 P-DSO-16-1 (SMD)
SDA 3302-5X Q67006-H5111 P-DSO-20-1 Tape & Reel (SMD)
SDA 3302-5X6 Q67006-H51 10 P-DSO-16-1 Tape & Reel (SMD)
Semiconductor Group
SI] EM IENS SDA 3302 Family
FunctionalDescription
Combined with a VCO (tuner) the SDA 3302 device, with four hardware-switched chip
addresses, forms a digitally programmable phase-locked loop for use in television sets with
PLL frequency-synthesis tuning.
The PLL permits precise crystal-controlled setting of the frequency of the tuner oscillators
between 16 and 1300 MHz in increments of 62.5 kHz. The tuning process is controlled by a
microprocessor via an PC bus. The crystal oscillator generates a sinusoidal signal suppressing
the higher-order harmonics, which reduces the moiré noise considerably.
Circuit Description
Tuning Section (refer to block diagram)
UHFNHF The tuner signal is capacitively coupled at the UHFNHF input and
REF subsequently amplified. The reference input REF should be decoupled to
ground using a capacitor of low series inductance. The signal passes
through an asynchronous divider with a fixed ratio of P = 8, an adjustable
divider with ratio N = 256 through 32767 and is then compared in a digital
phase/frequency detector to a reference frequency.) of 7.8125 kHz. The
latter is derived from a balanced, low-impedance 4 MHz crystal oscillator
Q1, Q2 (pin Q1, Q2), whose output signal is divided by Q = 512.
The phase detector has two outputs UP and DOWN that drive the two current
sources f+ and f- of a charge pump. Ifthe negative edge of the divided VCO
signal appears prior to the negative edge of the reference signal, the 1+
current source pulses for the duration of the phase difference. In the reverse
case the f- current source pulses.
PD, UD When the two signals are in phase, the charge-pump output (PD) goes high-
impedance (PLL is locked). An active low-pass filter integrates the current
pulses to generate the tuning voltage for the VCO (internal amplifier an
external transistor at the UD output and an external RC circuitry). The
charge-pump output can also be set to high-impedance state when control
bit T0 = 1. Here it should be noted, however, that the tuning voltage can alter
over a long period in the high-impedance state as a result of self-discharge
in the peripheral circuitry. UD can be disconnected internally by the control
bit os to enable external adjustments.
By means of a control bit 5l the pump current can be switched between two
values by software. This switchover permits alteration of the control
response of the PLL in the locked-in state. In this way different VCO gains in
the different TV bands can be compensated for example.
Semiconductor Group 2
