SCC2691AC1A28 ,Universal asynchronous receiver/transmitter (UART)PIN CONFIGURATIONSThe Philips Semiconductors SCC2691 Universal AsynchronousReceiver/Transmitter (UA ..
SCC2691AC1D24 ,Universal asynchronous receiver/transmitter (UART)BLOCK DIAGRAMINTERNAL DATABUS8D0–D7 BUS BUFFERCHANNEL ATRANSMITTxDHOLDING REGOPERATION CONTROLRDNWR ..
SCC2691AC1D24 ,Universal asynchronous receiver/transmitter (UART)FEATURES12 18• Full-duplex asynchronous receiver/transmitterPin Symbol Pin Symbol• Quadruple buffer ..
SCC2691AC1D24 ,Universal asynchronous receiver/transmitter (UART)BLOCK DIAGRAMINTERNAL DATABUS8D0–D7 BUS BUFFERCHANNEL ATRANSMITTxDHOLDING REGOPERATION CONTROLRDNWR ..
SCC2691AC1D24 ,Universal asynchronous receiver/transmitter (UART)INTEGRATED CIRCUITSSCC2691Universal asynchronousreceiver/transmitter (UART)Product specification 19 ..
SCC2691AC-1D24 ,Universal asynchronous receiver/transmitter (UART)Pin Configurations– Non-standard user-defined rate derived from programmabletimer/ counter• Single ..
SFW9520 ,Advanced Power MOSFETFEATURESBV = -100 VDSS Avalanche Rugged TechnologyΩR = 0.6DS(on) Rugged Gate Oxide Te ..
SFW9520TM ,100V P-Channel A-FETFEATURESBV = -100 VDSSn Avalanche Rugged TechnologyΩR = 0.6 DS(on) n Rugged Gate Oxide Tech ..
SFW9540 ,Advanced Power MOSFETFEATURESBV = -100 VDSS Avalanche Rugged TechnologyΩR = 0.2DS(on) Rugged Gate Oxide Te ..
SFW9540TM ,100V P-Channel A-FETFEATURESBV = -100 VDSSn Avalanche Rugged TechnologyΩR = 0.2DS(on) n Rugged Gate Oxide Techn ..
SFW9624 ,Advanced Power MOSFETFEATURESBV = -250 VDSS Avalanche Rugged TechnologyR = 2.4 ΩDS(on) Rugged Gate Oxide T ..
SFW9624TM ,250V P-Channel A-FETFEATURESBV = -250 VDSS Avalanche Rugged TechnologyR = 2.4 ΩDS(on) Rugged Gate Oxide T ..
SCC2691AC1A28-SCC2691AC1D24-SCC2691AC-1D24-SCC2691AC1D24.-SCC2691AE1A28-SCC2691AE1N24
Universal asynchronous receiver/transmitter (UART)
Product specification
Supersedes data of 1995 May 01
IC19 Data Handbook
1998 Sep 04
Philips Semiconductors Product specification
SCC2691Universal asynchronous receiver/transmitter (UART)
DESCRIPTIONThe Philips Semiconductors SCC2691 Universal Asynchronous
Receiver/Transmitter (UART) is a single-chip CMOS-LSI
communications device that provides a full-duplex asynchronous
receiver/transmitter. It is fabricated with Philips Semiconductors
CMOS technology which combines the benefits of high density and
low power consumption.
The operating speed of the receiver and transmitter can be selected
independently as one of 18 fixed baud rates, a 16X clock derived
from a programmable counter/timer, or an external 1X or 16X clock.
The baud rate generator and counter/timer can operate directly from
a crystal or from external clock inputs. The ability to independently
program the operating speed of the receiver and transmitter make
the UART particularly attractive for dual-speed channel applications
such as clustered terminal systems.
The receiver is quadruple buffered to minimize the potential of
receiver overrun or to reduce interrupt overhead in interrupt driven
systems. In addition, a handshaking capability is provided to disable
a remote UART transmitter when the receiver buffer is full.
The UART provides a power-down mode in which the oscillator is
frozen but the register contents are stored. This results in reduced
power consumption on the order of several magnitudes.
The UART is fully TTL compatible and operates from a single +5V
power supply.
FEATURES Full-duplex asynchronous receiver/transmitter Quadruple buffered receiver data register Programmable data format:
5 to 8 data bits plus parity
Odd, even, no parity or force parity
1, 1.5 or 2 stop bits programmable in 1/16-bit increments 16-bit programmable Counter/Timer Baud rate for the receiver and transmitter selectable from:
22 fixed rates: 50 to 115.2K baud
Non-standard rates to 115.2kb
Non-standard user-defined rate derived from programmable
timer/ counter
External 1X or 16X clock Parity, framing, and overrun detection False start bit detection Line break detection and generation Programmable channel mode
Normal (full-duplex)
Automatic echo
Local loopback
Remote Loopback Multi-function programmable 16-bit counter/timer
PIN CONFIGURATIONS
Figure 1. Pin Configurations Single interrupt output with seven maskable interrupting
conditions On-chip crystal oscillator Low power mode TTL compatible Single +5V power supply Commercial
(0°C to +70°C) and industrial (-40°C to +85°C)temperature versions available SOL, PLCC and 300 mil wide DIP packages available
Philips Semiconductors Product specification
SCC2691Universal asynchronous receiver/transmitter (UART)
ORDERING INFORMATION
BLOCK DIAGRAM
Figure 2. Block Diagram
Philips Semiconductors Product specification
SCC2691Universal asynchronous receiver/transmitter (UART)
PIN DESCRIPTION
Philips Semiconductors Product specification
SCC2691Universal asynchronous receiver/transmitter (UART)
ABSOLUTE MAXIMUM RATINGS1
NOTES: Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other condition above those indicated in the operation section of this specification is not
implied. For operating at elevated temperature, the device must be derated based on +150°C maximum junction temperature. This product includes circuitry specifically designed for the protection of its internal devices from damaging effects of excessive static
charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying any voltages larger than the rated maxima. Parameters are valid over specified temperature range. See Ordering Information table for applicable operating temperature and VCC supply
range.
DC ELECTRICAL CHARACTERISTICS1, 2, 3
NOTES: Parameters are valid over specified temperature range. See Ordering Information table for applicable operating temperature and VCC supply
range. All voltage measurements are referenced to ground (GND). For testing, all input signals swing between 0V and 3.0V with a transition time of
20ns max. For X1/CLK, this swing is between 0.4V and 4.0V. All time measurements are referenced at input voltages of 0.8V and 2V and
output voltages of 0.8V and 2V as appropriate. Typical values are at +25°C, typical supply voltages, and typical processing parameters. Test condition for outputs: CL = 150pF, except interrupt outputs. Test conditions for interrupt outputs: CL = 50pF, RL = 2.7kΩ to VCC. For power down current levels in the 1μA region see the UART application note.
Philips Semiconductors Product specification
SCC2691Universal asynchronous receiver/transmitter (UART)
AC ELECTRICAL CHARACTERISTICS1, 2, 3, 4
NOTES: Parameters are valid over specified temp. range. See Ordering Information table for applicable operating temp. and VCC supply range. All voltage measurements are referenced to ground (GND). For testing, all input signals swing between 0V and 3.0V with a transition time of
20ns max. For X1/CLK, this swing is between 0.4V and 4.0V. All time measurements are referenced at input voltages of 0.8V and 2V and
output voltages of 0.8V and 2V as appropriate. Typical values are at +25°C, typical supply voltages, and typical processing parameters. Test condition for outputs: CL = 150pF, except interrupt outputs. Test conditions for interrupt outputs: CL = 50pF, RL = 2.7kΩ to VCC. Timing is illustrated and referenced to the WRN and RDN inputs. The device may also be operated with CEN as the ‘strobing’ input. In this
case, all timing specifications apply referenced to the falling and rising edges of CEN. CEN and RDN (also CEN and WRN) are ORed inter-
nally. As a consequence, this signal asserted last initiates the cycle and the signal negated first terminates the cycle.
Philips Semiconductors Product specification
SCC2691Universal asynchronous receiver/transmitter (UART)
BLOCK DIAGRAMAs shown in the block diagram, the UART consists of: data bus buffer,
interrupt control, operation control, timing, receiver and transmitter.
Data Bus BufferThe data bus buffer provides the interface between the external and
internal data busses. It is controlled by the operation control block to
allow read and write operations to take place between the controlling
CPU and UART.
Interrupt ControlA single interrupt output (INTRN) is provided which may be asserted
upon occurrence of any of the following internal events:
Transmit holding register ready
Transmit shift register empty
Receive holding register ready or FIFO full
Change in break received status
Counter reached terminal count
Change in MPI input
Assertion of MPI input
Associated with the interrupt system are the interrupt mask register
(IMR) and the interrupt status register (ISR). The IMR can be
programmed to select only certain of the above conditions to cause
INTRN to be asserted. The ISR can be read by the CPU to
determine all currently active interrupting conditions. However, the
bits of the ISR are not masked by the IMR.
Operation ControlThe operation control logic receives operation commands from the
CPU and generates appropriate signals to internal sections to
control device operation. It contains address decoding and read and
write circuits to permit communications with the microprocessor via
the data bus buffer. The functions performed by the CPU read and
write operations are shown in Table 1.
Table 1. Register AddressingSCC2692, SCC68681 and SCC2698B” Philips Semiconductors ICs
for Data Communications, IC-19, 1994.
Mode registers 1 and 2 are accessed via an auxiliary pointer. The
pointer is set to MR1 by RESET or by issuing a reset pointer
command via the command register. Any read or write of the mode
register while the pointer is at MR1 switches the pointer to MR2. the
pointer then remains at MR2 so that subsequent accesses are to
MR2, unless the pointer is reset to MR1 as described above.
Timing CircuitsThe timing block consists of a crystal oscillator, a baud rate
generator, a programmable 16-bit counter/timer, and two clock
selectors.
The crystal oscillator operates directly from a 3.6864MHz crystal
connected across the X1/ CLK and X2 inputs with a minimum of
external components. If an external clock of the appropriate
frequency is available, it may be connected to X1/CLK. If an external
clock is used instead of a crystal, X1/CLK is driven using a
configuration similar to the one in Figure 7. In this case, the input
high-voltage must be capable of attaining the voltage specified in the
DC Electrical Characteristics. The clock serves as the basic timing
reference for the baud rate generator (BRG), the counter/timer, and
other internal circuits. A clock frequency, within the limits specified in
the electrical specifications, must be supplied if the internal BRG is
not used.
The baud rate generator operates from the oscillator or external
clock input and is capable of generating 18 commonly used data
communications baud rates ranging from 50 to 38.4K baud. Thirteen
of these are available simultaneously for use by the receiver and
transmitter. Eight are fixed, and one of two sets of five can be
selected by programming ACR[7]. The clock outputs from the BRG
are at 16X the actual baud rate. The counter/timer can be used as a
timer to produce a 16X clock for any other baud rate by counting
down the crystal clock or an external clock. The clock selectors
allow the independent selection by the receiver and transmitter of
any of these baud rates or an external timing signal.
Counter/Timer (C/T)The C/T operation is programmed by ACR[6:4]. One of eight timing
sources can be used as the input to the C/T. The output of the C/T is
available to the clock selectors and can be programmed by
ACR[2:0} to be output on the MPO pin.
In the timer mode, the C/T generates a square wave whose period is
twice the number of clock periods loaded into the C/T upper and
lower registers. The counter ready bit in the ISR is set once each
cycle of the square wave. If the value in CTUR or CTLR is changed,
the current half-period will not be affected, but subsequent
half-periods will be affected. In this mode the C/T runs continuously
and does not recognize the stop counter command (the command
only resets the counter ready bit in the ISR). Receipt of a start C/T
command causes the counter to terminate the current timing cycle
and to begin a new cycle using the values in CTUR and CTLR.
In the counter mode, the C/T counts down the number of pulses
loaded into CTUR and CTLR. Counting begins upon receipt of a
start C/T command. Upon reaching terminal count, the counter
ready bit in the ISR is set. The counter continues counting past the
terminal count until stopped by the CPU. If MPO is programmed to
Philips Semiconductors Product specification
SCC2691Universal asynchronous receiver/transmitter (UART)
values of CTUR and CTLR at any time, but the new count becomes
effective only on the next start counter command following a stop
counter command. If new values have not been loaded, the previous
count values are preserved and used for the next count cycle.
In the counter mode, the current value of the upper and lower eight
bits of the counter may be read by the CPU. It is recommended that
the counter be stopped when reading to prevent potential problems
which may occur if a carry from the lower eight bits to the upper
eight bits occurs between the times that both halves of the counter
are read. However, a subsequent start counter command causes
the counter to begin a new count cycle using the values in CTUR
and CTLR. See further description in CTUR/CTLR section.
Receiver and TransmitterThe UART is a full-duplex asynchronous receiver/transmitter. The
operating frequency for the receiver and transmitter can be selected
independently from the baud rate generator, the counter/timer, or
from an external input. Registers associated with the
communications channel are: the mode registers (MR1 and MR2),
the clock select register (CSR), the command register (CR), the
status register (SR), the transmit holding register (THR), and the
receive holding register (RHR).
TransmitterThe transmitter accepts parallel data from the CPU and converts it
to a serial bit stream on the TxD output pin. It automatically sends a
start bit followed by the programmed number of data bits, an
optional parity bit, and the programmed number of stop bits. The
least significant bit is sent first. Following the transmission of the
stop bits, if a new character is not available in the THR, the TxD
output remains high and the TxEMT bit in the SR will be set to 1.
Transmission resumes and the TxEMT bit is cleared when the CPU
loads a new character in the THR. In the 16X clock mode, this also
resynchronizes the internal 1X transmitter clock so that transmission
of the new character begins with minimum delay.
The transmitter can be forced to send a break (continuous low
condition) by issuing a start break command via the CR. The break
is terminated by a stop break command.
If the transmitter is disabled, it continues operating until the
character currently being transmitted and the character in the THR,
if any, are completely sent out. Characters cannot be loaded in the
THR while the transmitter is disabled.
ReceiverThe receiver accepts serial data on the RxD pin, converts the serial
input to parallel format, checks for start bit, stop bit, parity bit (if any),
or break condition, and presents the assembled character to the
CPU. The receiver looks for a high-to-low (mark-to-space) transition
of the start bit on the RxD input pin. If a transition is detected, the
state of the RxD pin is sampled again each 16X clock for 7-1/2
clocks (16X clock mode) or at the next rising edge of the bit time
clock (1X clock mode). If RxD is sampled high, the start bit is invalid
and the search for a valid start bit begins again. If RxD is still low, a
valid start bit is assumed and the receiver continues to sample the
input at one bit time intervals at the theoretical center of the bit, until
the proper number of data bits and the parity bit (if any) have been
assembled, and one sop bit has been detected. The data is then
transferred to the RHR and the RxRDY bit in the SR is set to a 1. If
the character length is less than eight bits, the most significant
one-half of the bit period after the stop bit was sampled, then the
receiver operates as if a new start bit transition had been detected at
that point(one-half bit time after the stop bit was sampled).
The parity error, framing error and overrun error (if any) are strobed
into the SR at the received character boundary, before the RxRDY
status bit is set.
If a break condition is detected (RxD is low for the entire character
including the stop bit), only one character consisting of all zeros will
be loaded in the FIFO and the received SR break bit is set to 1. The
RxD input must return to high for two (2) clock edges of the X1
crystal clock for the receiver to recognize the end of the break
condition and begin the search for a start bit. This will usually
require a high time of one X1 clock period or 3 X1 edges since
the clock of the controller is not synchronous to the X1 clock.
RECEIVER FIFOThe RHR consists of a first-in-first-out (FIFO) queue with a capacity
of three characters. Data is loaded from the receive shift register
into the top-most empty position of the FIFO. The RxRDY bit in the
status register (SR) is set whenever one or more characters are
available to be read, and a FFULL status bit is set if all three queue
positions are filled with data. Either of these bits can be selected to
cause an interrupt. A read of the RHR outputs the data at the top of
the FIFO. After the read cycle, the data FIFO and its associated
status bits are ‘popped’ thus emptying a FIFO position for new data.
Receiver Status BitsIn addition to the data word, three status bits (parity error, framing
error, and received break) are appended to each data character in
the FIFO. Status can be provided in two ways, as programmed by
the error mode control bit in mode register 1. In the character mode,
status is provided on a character-by-character basis: the status
applies only to the character at the top of the FIFO. In the block
mode, the status provided in the SR for these three bits is the
logical-OR of the status for all characters coming to the top of the
FIFO since the last reset error command was issued. In either
mode, reading the SR does not affect the FIFO. The FIFO is
‘popped’ only when the RHR is read. Therefore, the SR should be
read prior to reading the corresponding data character.
The receiver can control the deactivation of RTS. If programmed to
operate in this mode, the RTSN output will be negated when a valid
start bit was received and the FIFO is full. When a FIFO position
becomes available, the RTSN output will be re-asserted
automatically. This feature can be used to prevent an overrun, in
the receiver, by connecting the RTSN output to the CTSN input of
the transmitting device.
Receiver Reset and DisableReceiver disable stops the receiver immediately – data being
assembled if the receiver shift register is lost. Data and status in the
FIFO is preserved and may be read. A re-enable of the receiver
after a disable will cause the receiver to begin assembling
characters at the next start bit detected. A receiver reset will discard
the present shift register data, reset the receiver ready bit (RxRDY),
clear the status of the byte at the top of the FIFO and re-align the
FIFO read/write pointers. This has the appearance of “clearing or
flushing” the receiver FIFO. In fact, the FIFO is NEVER cleared!
The data in the FIFO remains valid until overwritten by another
received character. Because of this, erroneous reading or extra
Philips Semiconductors Product specification
SCC2691Universal asynchronous receiver/transmitter (UART)
In addition to the normal transmitter and receiver operation
described above, the UART incorporates a special mode which
provides automatic wake-up of the receiver through address frame
recognition for multi-processor communications. This mode is
selected by programming bits MR1[4:3] to ‘11’.
In this mode of operation, a ‘master’ station transmits an address
character followed by data characters for the addressed ‘slave’
station. The slave stations, whose receivers are normally disabled,
examine the received data stream and ‘wake-up’ the CPU [by
setting RxRDY) only upon receipt of an address character. The CPU
compares the received address to its station address and enables
the receiver if it wishes to receive the subsequent data characters.
Upon receipt of another address character, the CPU may disable the
receiver to initiate the process again.
A transmitted character consists of a start bit, the programmed
number of data bits, an address/data (A/D) bit, and the programmed
number of stop bits. The polarity of the transmitted A/D bit is
selected by the CPU by programming bit MR1[2]. MR1[2] = 0
transmits a zero in the A/D bit position which identifies the
corresponding data bits as data, while MR1[2] = 1 transmits a one in
the A/D bit position which identifies the corresponding data bits as
an address. The CPU should program the mode register prior to
loading the corresponding data bits in the THR.
While in this mode, the receiver continuously looks at the received
data stream, whether it is enabled or disabled. If disabled, it sets the
RxRDY status bit and loads the character in the RHR FIFO if the
received A/D bit is a one, but discards the received character if the
received A/D bit is a zero. If enabled, all received characters are
then transferred to the CPU via the RHR. In either case, the data
bits are loaded in the data FIFO while the A/D bit is loaded in the
status FIFO position normally used for parity error (SR[5]). Framing
error, overrun error, and break detect operate normally whether or
not the receiver is enabled.
MULTI-PURPOSE INPUT PINThe MPI pin can be programmed as an input to one of several
UART circuits. The function of the pin is selected by programming
the appropriate control register (MR2[4]), ACR[6:4], CSR [7:4, 3:0]}.
Only one of the functions may be selected at any given time. If CTS
or GPI is selected, a change of state detector provided with the pin
is activated. A high-to-low or low-to-high transition of the inputs
lasting longer than 25–50μs sets the MPI change-of-state bit in the
interrupt status register. The bit is cleared via a command. The
change-of-state can be programmed to generate an interrupt to the
CPU by setting the corresponding bit in the interrupt mask register.
The input port pulse detection circuitry uses a 38.4kHz sampling
clock derived from one of the baud rate generator taps. This
produces a sampling period of slightly more than 25μs (assuming a
3.6864MHz oscillator input). The detection circuitry, in order to
guarantee that a true change in level has occurred, requires two
successive samples at the new logic level be observed. As a
consequence, the minimum duration of the signal change is 25μs if
the transition occurs coincident with the first sample pulse. The 50μs
time refers to the condition where the change of state is just missed
and the first change of state is not detected until after an additional
25μs. The MPI pin has a small pull-up device that will source 1 to
4 A of current from VCC. This pin does not require pull-up devices
or VCC connection if it is not used.
MULT-PURPOSE OUTPUT PINThis pin can be programmed to serve as a request-to-send output,
the counter/timer output, the output for the 1X or 16X transmitter or
receiver clocks, the TxRDY output or the RxRDY/FFULL output (see
ACR[2:0] – MPO Output Select). Please note that this pin drives
both high and low. HOWEVER when it is programmed to represent
interrupt type functions (such as receiver ready, transmitter ready or
counter/timer ready) it will be switched to an open drain
configuration in which case an external pull-up device would be
required.
REGISTERSThe operation of the UART is programmed by writing control words
in the appropriate registers. Operational feedback is provided via
status registers which can be read by the CPU. Addressing of the
registers is as described in Table 1.
The contents of certain control registers are initialized to zero on
reset (see RESET pin description). Care should be exercised if the
contents of a register are changed during operation, since certain
changes may cause operational problems. For example, changing
the number of bits per character while the transmitter is active may
cause the transmission of an incorrect character. The contents of
the MR, the CSR, and the ACR should only be changed while the
receiver and transmitter are disabled, and certain changes to the
ACR should only be made while the C/T is stopped. The bit formats
of the UART are shown in Table 2.
MR1 – Mode Register 1MR1 is accessed when the MR pointer points to MR1. The pointer is
set to MR1 by RESET or by a set pointer command applied via the
CR. After reading or writing MR1, the pointers are set at MR2.
MR1[7] – Receiver Request-to-Send ControlThe bit controls the deactivation of the RTSN output (MPO) by the
receiver. This output is normally asserted and negated by
commands applied via the command register. MR1[7] = 1 causes
RTSN to be automatically negated upon receipt of a valid start bit if
the receiver FIFO is full. RTSN is reasserted when an empty FIFO
position is available. This feature can be used to prevent overrun in
the receiver by using the RTSN output signal to control the CTS
input of the transmitting device.
MR1[6] – Receiver Interrupt SelectThis bit selects either the receiver ready status (RxRDY) or the FIFO
full status (FFULL) to be used for CPU interrupts.
MR1[5] – Error Mode SelectThis bit selects the operating mode of the three FIFOed status bits
(FE, PE, received break). In the character mode, status is provided
on a character-by-character basis. The status applies only to the
character at the top of the FIFO. In the block mode, the status
provided in the SR for these bits is the accumulation (logical-OR) of
the status for all characters coming to the top of the FIFO since the
last reset error command was issued.
MR1[4:3] – Parity Mode SelectIf with parity or force parity is selected, a parity bit is added to the
transmitted character and the receiver performs a parity check on
incoming data. MR![4:3] = 11 selects the channel to operate in the
special wake-up mode.
MR1[2] – Parity Type Select
Philips Semiconductors Product specification
SCC2691Universal asynchronous receiver/transmitter (UART)
parity mode is programmed. In the special wake-up mode, it selects
the polarity of the transmitted A/D bit.
MR1[1:0] – Bits Per Character SelectThis field selects the number of data bits per character to be
transmitted and received. The character length does not include the
start, parity, and stop bits.
MR2 – Mode Register 2MR2 is accessed when the channel MR pointer points to MR2,
which occurs after any access to MR1. Accesses to MR2 do not
change the pointer.
MR2[7:6] – Mode SelectThe UART can operate in one of four modes. MR2[7:6] = 00 is the
normal mode, with the transmitter and receiver operating
independently. MR2[7:6] = 01 places the channel in the automatic
echo mode, which automatically re-transmits the received data. The
following conditions are true while in automatic echo mode: Received data is re-clocked and retransmitted on the TxD
output. The receive clock is used for the transmitter. The receiver must be enabled, but the transmitter need not be
enabled. The TxRDY and TxEMT status bits are inactive. The received parity is checked, but is not regenerated for
transmission, i.e., transmitted parity bit is as received. Character framing is checked, but the stop bits are retransmitted
as received. A received break is echoed as received until the next valid start
bit is detected. CPU-to-receiver communication continues normally, but the
CPU-to-transmitter link is disabled.
Two diagnostic modes can also be selected. MR2[7:6] = 10 selects
local loopback mode. In this mode: The transmitter output is internally connected to the receiver
input. The transmit clock is used for the receiver. The TxD output is held high. The RxD input is ignored. The transmitter must be enabled, but the receiver need not be
enabled. CPU to transmitter and receiver communications continue
normally.
The second diagnostic mode is the remote loopback mode, selected
by MR2[7:6] = 11. In this mode: Received data is re-clocked and retransmitted on the TxD
output. The receive clock is used for the transmitter. Received data is not sent to the local CPU, and the error status
conditions are inactive. The received parity is not checked and is not regenerated for
transmission, i.e., the transmitted parity bit is as received. The receiver must be enabled, but the transmitter need not be
enabled. Character framing is not checked, and the stop bits are
retransmitted as received. A received break is echoed as received until the next valid start
bit is detected.
immediately. An exception to this is switching out of auto-echo or
remote loopback modes; if the deselection occurs just after the
receiver has sampled the stop bit (indicated in auto-echo by
assertion o fRxRDY), and the transmitter is enabled, the transmitter
is enabled, the transmitter will remain in auto-echo mode until one
full stop bit has been retransmitted.
MR2[5] – Transmitter Request-to–Send ControlCAUTION: When the transmitter controls the OP pin (usually used
for the RTSN signal) the meaning of the pin is not RTSN at all!
Rather, it signals that the transmitter has finished the transmission
(i.e., end of block).
This bit allows deactivation of the RTSN output by the transmitter.
This output is manually asserted and negated by the appropriate
commands issued via the command register. MR2[5] set to 1
caused the RTSN to be reset automatically one bit time after the
character(s) in the transmit shift register and in the THR (if any) are
completely transmitted (including the programmed number of stop
bits) if a previously issued transmitter disable is pending. This
feature can be used to automatically terminate the transmission as
follows: Program the auto-reset mode: MR2[5]=1 Enable transmitter, if not already enabled Assert RTSN via command Send message After the last character of the message is loaded to the THR,
disable the transmitter. (If the transmitter is underrun, a special
case exists. See note below.) The last character will be transmitted and the RTSN will be reset
one bit time after the last stop bit is sent.
NOTE: The transmitter is in an underrun condition when both the
TxRDY and the TxEMT bits are set. This condition also exists
immediately after the transmitter is enabled from the disabled or
reset state. When using the above procedure with the transmitter in
the underrun condition, the issuing of the transmitter disable must be
delayed from the loading of a single, or last, character until the
TxRDY becomes active again after the character is loaded.
MR2[4] – Clear-to-Send ControlThe sate of this bit determines if the CTSN input (MPI) controls the
operation of the transmitter. If this bit is 0, CTSN has no effect on the
transmitter. If this bit is a 1, the transmitter checks the sate of CTSN
each time it is ready to send a character. If it is asserted (low), the
character is transmitted. If it is negated (high), the TxD output
remains in the marking state and the transmission is delayed until
CTSN goes low. Changes in CTSN while a character is being
transmitted do not affect the transmission of that character. This
feature can be used to prevent overrun of a remote receiver.
MR2[3:0] – Stop Bit Length SelectThis field programs the length of the stop bit appended to the
transmitted character. Stop bit lengths of 9/16 to 1 and 1–9/16 to 2
bits, in increments of 1/16 bit, can be programmed for character
lengths of 6, 7, and 8 bits. For a character length of 5 bits, 1–1/16 to
2 stop bits can be programmed in increments of 1/16 bit. In all
cases, the receiver only checks for a mark condition at the center of
the first stop bit position (one bit time after the last data bit, or after
the parity bit if parity is enabled). If an external 1X clock is used for
the transmitter, MR2[3] = 0 selects one stop bit and MR2[3] = 1
selects two stop bits to be transmitted.
Philips Semiconductors Product specification
SCC2691Universal asynchronous receiver/transmitter (UART)
Table 2. Register Bit Formats
Philips Semiconductors Product specification
SCC2691Universal asynchronous receiver/transmitter (UART)
Table 2. Register Bit Formats (Continued)
CSR – Clock Select Register (see Table 6. also)
Table 3. Baud Rate SelectionSee “Extended baud rates for SCN2681, SCN68681, SCC2691,
SCC2692, SCC68681 and SCC2698B” in application notes
elsewhere in this publication
CSR[7:4] – Receiver Clock SelectThis field selects the baud rate clock for the receiver as shown in
Table 3. The baud rates listed are for a 3.6864MHz crystal or
external clock.
CSR[3:0] – Transmitter Clock SelectThis field selects the baud rate clock for the transmitter. The field
definition is as shown in Table 3.
CR – Command RegisterCR is used to write commands to the UART. Multiple commands can
be specified in a single write to CR as long as the commands are
non-conflicting, e.g., the enable transmitter and reset transmitter
commands cannot be specified in a single command word.
CR[7:4] – Miscellaneous CommandsThe encoded value of this field may be used to specify a single
command as follows:
NOTE: Access to the upper four bits of the command register
should be separated by three (3) edges of the X1 clock.
0000 No command.
0001 Reset MR pointer. Causes the MR pointer to point to MR1.
0011 Reset transmitter. Resets the transmitter as if a hardware reset
had been applied
0100 Reset error status. Clears the received break, parity error,
framing error, and overrun error bits in the status
register (SR[7:4]}. Used in character mode to clear OE status
(although RB, PE, and FE bits will also be cleared), and in
block mode to clear all error status after a block of data has
been received.
0101 Reset break change interrupt. Causes the break detect change
bit in the interrupt status register (ISR[3]) to be cleared to zero.
0110 Start break. Forces the TxD output low (spacing). If the
transmitter is empty, the start of the break condition will be
delayed up to two bit times. If the transmitter is active, the
break begins when transmission of the character is completed.
If a character is in the THR, the start of break is delayed until
that character or any others loaded after it have been
transmitted (TxEMT must be true before break begins). The
transmitter must be enabled to start a break
0111 Stop break. The TxD line will go high (marking) within two bit
times. TxD will remain high for one bit time before the next
character, if any, is transmitted.
1000 Start C/T. In counter or timer modes, causes the contents of
CTUR/CTLR to be preset into the counter/timer and starts the
counting cycle. In timer mode, any counting cycle in progress
when the command is issued is terminated. In counter mode,
has no effect unless a stop C/T command was issued
previously.
1001 Stop counter. In counter mode, stops operation of the
counter/timer, resets the counter ready bit in the ISR, and
forces the MPO output high if it is programmed to be the
output of the C/T. In timer mode, resets the counter ready bit in
the ISR but has no effect on the counter/timer itself or on the
MPO output.
1010 Assert RTSN. Causes the RTSN output (MPO) to be asserted
(low).
1011 Negate RTSN.Causes the RTSN output (MPO) to be negated
(high).
1100 Reset MPI change interrupt. Causes the MPI change bit in the
interrupt status register (ISR[7]) to be cleared to zero.
1100 Reserved.
111x Reserved.
CR[3] – Disable TransmitterThis command terminates operation and resets the TxRDY and
TxEMT status bits. However, if a character is being transmitted or if
a character is in the THR when the transmitter is disabled, the
transmission of the character(s) is completed before assuming the
inactive state. A disabled transmitter cannot be loaded.
