SCANSTA101SM ,Low Voltage IEEE 1149.1 STA Masterfeatures of theSTA101 further allow it to offload some of the processor n Uses generic, asynchronou ..
SCANSTA101SM/NOPB ,Low Voltage IEEE 1149.1 System Test Access (STA) Master 49-NFBGA -40 to 85FEATURES DESCRIPTIONThe SCANSTA101 is designed to function as a test2• Compatible with IEEE Std. 11 ..
SCANSTA101SMX/NOPB ,Low Voltage IEEE 1149.1 System Test Access (STA) Master 49-NFBGA -40 to 85 SNLS057J –MAY 2002–REVISED APRIL 2013CONNECTION DIAGRAMFigure 2. NFBGA Package Pinout(Top View)PIN ..
SCANSTA111MT ,Enhanced SCAN bridge Multidrop Addressable IEEE 1149.1 (JTAG) PortSCANSTA111 Enhanced SCAN bridge Multidrop Addressable IEEE 1149.1 (JTAG) PortApril 2004SCANSTA111En ..
SCANSTA111MTX ,Enhanced SCAN bridge Multidrop Addressable IEEE 1149.1 (JTAG) PortGeneral Descriptionn Mode Register allows local TAPs to be bypassed,0The SCANSTA111 extends the IEE ..
SCANSTA111SM ,Enhanced SCAN bridge Multidrop Addressable IEEE 1149.1 (JTAG) PortFeaturesallow an alternate test master to take control of the localTAPs (LSP have a TRI-STATE notif ..
SFS9620 ,Advanced Power MOSFETFEATURESBV = -200 VDSS Avalanche Rugged TechnologyR = 1.5 ΩDS(on) Rugged Gate Oxide T ..
SFS9624 ,Advanced Power MOSFETFEATURESBV = -250 VDSS Avalanche Rugged TechnologyR = 2.4 ΩDS(on) Rugged Gate Oxide T ..
SFS9630 ,Advanced Power MOSFETFEATURESBV = -200 VDSS Avalanche Rugged TechnologyR = 0.8 ΩDS(on) Rugged Gate Oxide T ..
SFS9634 ,Advanced Power MOSFETSFS9634Advanced Power MOSFET
SFS9634. ,Advanced Power MOSFETSFS9634Advanced Power MOSFET
SFS9644 ,Advanced Power MOSFETFEATURESBV = -250 VDSS Avalanche Rugged TechnologyR = 0.8 ΩDS(on) Rugged Gate Oxide T ..
SCANSTA101SM
Low Voltage IEEE 1149.1 STA Master
SCANSTA101
Low Voltage IEEE 1149.1 STA Master
General DescriptionThe SCANSTA101is designedto functionasa test master
fora IEEE 1149.1 test system. The minimal requirementsto
createa tester area microcomputer (uP, RAM/ROM, clock,
etc.), SCANEASE r2.0 software, anda STA101.
The SCANSTA101isan enhanced versionof, and replace-
mentfor, the SCANPSC100. The additional featuresof the
STA101 further allowitto offload someof the processor
overhead while remaining flexible. The device architecture
supports IEEE 1149.1, BIST, and IEEE 1532. The flexibility
will allowitto adaptto any changes that may occurin 1532
and supportyet unknown variants.
The SCANSTA101is usefulin improving vector throughput
when applying serial vectorsto system test circuitry and
reduces the software overhead thatis associated with ap-
plying serial patterns witha parallel processor. The SCAN-
STA101 featuresa generic Parallel Processor Interface
(PPI) which operatesby serializing data fromthe parallel bus
for shifting through the chainof 1149.1 compliant compo-
nents (i.e., scan chain). Writes canbe controlled eitherby
wait statesorthe DTACK line. Handshakingis accomplished
with either pollingor interrupts.
Features Compatible with IEEE Std. 1149.1 (JTAG) Test Access
Port and Boundary Scan Architecture Supportedby National’s SCAN Ease (Embedded
Application Software Enabler) Software Rev 2.0 Availableasa Silicon Device and Intellectual Property
(IP) modelfor embedding into VLSI devices Uses generic, asynchronous processor interface;
compatible witha wide rangeof processors and PCLK
frequencies 16-bit Data Interface(IP scalableto 32-bit) 2Kx32bit dual-port memory addressingfor accessby
the PPIor the 1149.1 master Load-on-the-fly (LotF) and Preload operating modes
supported On-Board Sequencer allows multi-vector operations
suchas those requiredto load data intoan FPGA On-Board Compares support TDI validation against
preloaded expected data 32-bit Linear Feedback Shift Register (LFSR)atthe Test
DataIn (TDI) port State, Shift, and BIST macros allow predetermined TMS
sequencestobe utilized Operatesat 3.3v supply voltagesw/5V tolerantI/O Outputs support Power-Down TRI-STATE mode.
SCANSTA101 ArchitectureFIGURE1.
January 2005
SCANST
A101
Low
oltage
IEEE
Master
