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Partno	Mfg	Dc	Qty	Available	Descript
SCANSTA101SM/NOPB |SCANSTA101SMNOPB	NS	N/a	4	avai	Low Voltage IEEE 1149.1 System Test Access (STA) Master 49-NFBGA -40 to 85
SCANSTA101SMX/NOPB |SCANSTA101SMXNOPB	NSC	N/a	590	avai	Low Voltage IEEE 1149.1 System Test Access (STA) Master 49-NFBGA -40 to 85

SCANSTA101SMX/NOPB ,Low Voltage IEEE 1149.1 System Test Access (STA) Master 49-NFBGA -40 to 85 SNLS057J –MAY 2002–REVISED APRIL 2013CONNECTION DIAGRAMFigure 2. NFBGA Package Pinout(Top View)PIN ..
SCANSTA111MT ,Enhanced SCAN bridge Multidrop Addressable IEEE 1149.1 (JTAG) PortSCANSTA111 Enhanced SCAN bridge Multidrop Addressable IEEE 1149.1 (JTAG) PortApril 2004SCANSTA111En ..
SCANSTA111MTX ,Enhanced SCAN bridge Multidrop Addressable IEEE 1149.1 (JTAG) PortGeneral Descriptionn Mode Register allows local TAPs to be bypassed,0The SCANSTA111 extends the IEE ..
SCANSTA111SM ,Enhanced SCAN bridge Multidrop Addressable IEEE 1149.1 (JTAG) PortFeaturesallow an alternate test master to take control of the localTAPs (LSP have a TRI-STATE notif ..
SCANSTA111SM ,Enhanced SCAN bridge Multidrop Addressable IEEE 1149.1 (JTAG) PortFeaturesallow an alternate test master to take control of the localTAPs (LSP have a TRI-STATE notif ..
SCANSTA112SM ,7-port Multidrop IEEE 1149.1 (JTAG) MultiplexerGeneral Descriptionn Bi-directional Backplane and LSP ports are0The SCANSTA112 extends the IEEE Std ..
SFS9620 ,Advanced Power MOSFETFEATURESBV = -200 VDSS Avalanche Rugged TechnologyR = 1.5 ΩDS(on) Rugged Gate Oxide T ..
SFS9624 ,Advanced Power MOSFETFEATURESBV = -250 VDSS Avalanche Rugged TechnologyR = 2.4 ΩDS(on) Rugged Gate Oxide T ..
SFS9630 ,Advanced Power MOSFETFEATURESBV = -200 VDSS Avalanche Rugged TechnologyR = 0.8 ΩDS(on) Rugged Gate Oxide T ..
SFS9634 ,Advanced Power MOSFETSFS9634Advanced Power MOSFET
SFS9634. ,Advanced Power MOSFETSFS9634Advanced Power MOSFET
SFS9644 ,Advanced Power MOSFETFEATURESBV = -250 VDSS Avalanche Rugged TechnologyR = 0.8 ΩDS(on) Rugged Gate Oxide T ..

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SCANSTA101SM/NOPB-SCANSTA101SMX/NOPB
Low Voltage IEEE 1149.1 System Test Access (STA) Master 49-NFBGA -40 to 85
SCANSTA101
www.ti.com SNLS057J–MAY 2002–REVISED APRIL 2013
SCANSTA101 Low Voltage IEEE 1149.1 System Test Access (STA) Master
Checkfor Samples: SCANSTA101
1FEATURES DESCRIPTION
The SCANSTA101is designedto function asa test Compatible with IEEE Std. 1149.1 (JTAG) Test master for an IEEE 1149.1 boundary scan testAccess Port and Boundary Scan Architecture system.Itis suitable for use in embedded IEEE• Supportedby Texas Instruments' SCAN Ease 1149.1 applications andasa componentina stand-(SCAN Embedded Application Software alone boundary scan tester.
Enabler) Software Rev 2.0 The SCANSTA101is an enhanced version of, anda• Uses Generic, Asynchronous Processor replacement for, the SCANPSC100. TheInterface; Compatible witha Wide Rangeof SCANSTA101 supports the IEEE 1149.1 Test AccessProcessors and Processor Clock (PCLK) Port (TAP) standard and the IEEE 1532 standard for
Frequencies in-system configurationof programmable devices. 16-Bit Data Interface (IP Scalableto 32-bit) The SCANSTA101 improves test vector throughput 2kx32 Bit Dual-Port Memory and reduces software overhead in the system
processor. The SCANSTA101 presentsa simple,• Load-on-the-Fly (LotF) and Preloaded Vector register-based interface to the system processor.Operating Modes Supported Texas Instruments provides C-language source code• On-Board Sequencer Allows Multi-Vector which can be includedin the embedded systemOperations suchas those Requiredto Load software. The combinationof the SCANSTA101 and
Data Intoan FPGA its support software comprisesa simple API for
boundary scan operations.• On-Board Compares Support Test DataIn
(TDI) Validation Against Preloaded Expected The interface from the SCANSTA101to the systemData processor is implemented by reading and writing
registers, some of which map to locationsin the• 32-Bit Linear Feedback Shift Register (LFSR)
SCANSTA101 memory. Hardware handshaking andat the Test DataIn (TDI) Port for Signature interrupt lines are provided as partof the processorCompression interface.• State, Shift, and BIST Macros Allow
The SCANSTA101is available asa stand-alonePredetermined Test Mode Select (TMS) device packagedina 49-pin NFBGA package.ItisSequencestobe Utilized also available as an IP macro for synthesis in• Operatesat 3.3V Supply Voltages with5V programmable logic devices.Tolerant I/O TRI-STATE