SCAN18373TSSCX ,Transparent Latch with 3-STATE OutputsFunctional DescriptionThe SCAN18373T consists of two sets of nine D-type the inputs a set-up time p ..
SCAN18374TSSC ,D Flip-Flop with 3-STATE Outputsapplicationsdard Test Access Port and BOUNDARY-SCAN Architec-ture with the incorporation of the def ..
SCAN18374TSSCX ,D Flip-Flop with 3-STATE OutputsFunctional DescriptionThe SCAN18374 consists of two sets of nine edge-trig- LOW-to-HIGH Clock (ACP ..
SCAN18540TSSC ,Inverting Line Driver with 3-STATE OutputsapplicationsTest Access Port and Boundary Scan Architecture with theincorporation of the defined bo ..
SCAN18540TSSC ,Inverting Line Driver with 3-STATE Outputsapplicationsnals. This device is compliant with IEEE 1149.1 Standard
SCAN18373TSSC-SCAN18373TSSCX
Transparent Latch with 3-STATE Outputs
SCAN18373T Transparent Latch with 3-STATE Outputs October 1991 Revised May 2000 SCAN18373T Transparent Latch with 3-STATE Outputs General Description Features The SCAN18373T is a high speed, low-power transparentIEEE 1149.1 (JTAG) Compliant latch featuring separate data inputs organized into dual 9-Buffered active-low latch enable bit bytes with byte-oriented latch enable and output enable 3-STATE outputs for bus-oriented applications control signals. This device is compliant with IEEE 1149.1 9-bit data busses for parity applications Standard Test Access Port and Boundary Scan Architec- ture with the incorporation of the defined boundary-scanReduced-swing outputs source 32 mA/sink 64 mA test logic and test access port consisting of Test Data InputGuaranteed to drive 50Ω transmission line to TTL input (TDI), Test Data Out (TDO), Test Mode Select (TMS), and levels of 0.8V and 2.0V Test Clock (TCK). TTL compatible inputs 25 mil pitch SSOP (Shrink Small Outline Package) Includes CLAMP and HIGHZ instructions Member of Fairchild’s SCAN Products Ordering Code: Order Number Package Number Package Description SCAN1837TSSC MS56A 56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300 Wide Device also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram Pin Descriptions Pin Names Description AI , BI Data Inputs (0–8) (0–8) ALE, BLE Latch Enable Inputs AOE , BOE 3-STATE Output Enable Inputs 1 1 AO , BO 3-STATE Latch Outputs (0–8) (0–8) Truth Tables Inputs AO (0–8) ALE AOE AI 1 (0–8) XH X Z HL L L HL H H LL X AO 0 Inputs BO (0–8) BOE BI BLE 1 (0–8) XH X Z HL L L HL H H LL X BO 0 H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = High Impedance AO = Previous AO before H-to-L transition of ALE 0 BO = Previous BO before H-to-L transition of BLE 0 © 2000 DS010962
