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SC28L92A1A-SC28L92A1B
3.3V-5.0V Dual Universal Asynchronous Receiver/Transmitter (DUART)
Product specification
Supersedes data of 1999 May 07
IC19 Data Handbook
2000 Jan 21
Philips Semiconductors Product specification
SC28L923.3V–5.0V Dual Universal Asynchronous
Receiver/Transmitter (DUART)
DESCRIPTION
The SC28L92 is a pin and function replacement for the SCC2692
and SC26C92 operating at 3.3 or 5 volts supply with added features
and deeper FIFOs. Its configuration on power up is that of the
SC26C92. Its differences from the 2692 are: 16 character receiver, 16
character transmit FIFOs, watch dog timer for each receiver, mode
register 0 is added, extended baud rate and overall faster speeds,
programmable receiver and transmitter interrupts. (Neither the
SC26C92 nor the SCC2692 is being discontinued.)
Pin programming will allow the device to operate with either the
Motorola or Intel bus interface. The bit 3 of the MR0a register allows
the device to operate in an 8 byte FIFO mode if strict compliance
with the SC26C92 FIFO structure is required.
The Philips Semiconductors SC28L92 Dual Universal Asynchronous
Receiver/Transmitter (DUART) is a single-chip CMOS-LSI
communications device that provides two full-duplex asynchronous
receiver/transmitter channels in a single package. It interfaces
directly with microprocessors and may be used in a polled or
interrupt driven system with modem and DMA interface.
The operating mode and data format of each channel can be
programmed independently. Additionally, each receiver and
transmitter can select its operating speed as one of 28 fixed baud
rates; a 16X clock derived from a programmable counter/timer, or an
external 1X or 16X clock. The baud rate generator and counter/timer
can operate directly from a crystal or from external clock inputs. The
ability to independently program the operating speed of the receiver
and transmitter make the DUART particularly attractive for
dual-speed channel applications such as clustered terminal
systems.
Each receiver and transmitter is buffered by 8 or 16 character FIFOs
to minimize the potential of receiver overrun, transmitter underrun
and to reduce interrupt overhead in interrupt driven systems. In
addition, a flow control capability is provided via RTS/CTS signaling
to disable a remote transmitter when the receiver buffer is full.
Also provided on the SC28L92 are a multipurpose 7-bit input port
and a multipurpose 8-bit output port. These can be used as general
purpose I/O ports or can be assigned specific functions (such as
clock inputs or status/interrupt outputs) under program control.
The SC28L92 is available in two package versions: a 44-pin PLCC
and 44-pin plastic quad flat pack (PQFP).
FEATURES Member of IMPACT family: 3.3 to 5.0 volt , –40°C to +85°C and
68K for 80xxx bus interface for all devices. Dual full-duplex independent asynchronous receiver/transmitters 16 character FIFOs for each receiver and transmitter Pin programming selects 68K or 80xxx bus interface Programmable data format 5 to 8 data bits plus parity Odd, even, no parity or force parity - 1, 1.5 or 2 stop bits programmable in 1/16-bit increments 16-bit programmable Counter/Timer Programmable baud rate for each receiver and transmitter
selectable from: 28 fixed rates: 50 to 230.4k baud Other baud rates to MHz at 16X Programmable user-defined rates derived from a programmable
counter/timer External 1X or 16X clock Parity, framing, and overrun error detection False start bit detection Line break detection and generation Programmable channel mode Normal (full-duplex) Automatic echo Local loop back Remote loop back Multi-drop mode (also called ‘wake-up’ or ‘9-bit’) Multi-function 7-bit input port (includes IACKN) Can serve as clock or control inputs Change of state detection on four inputs Inputs have typically >100k pull-up resistors Change of state detectors for modem control Multi-function 8-bit output port Individual bit set/reset capability Outputs can be programmed to be status/interrupt signals FIFO status for DMA interface Versatile interrupt system Single interrupt output with eight maskable interrupting
conditions Output port can be configured to provide a total of up to six
separate interrupt outputs that may be wire ORed. Each FIFO can be programmed for four different interrupt levels Watch dog timer for each receiver Maximum data transfer rates:
1X – 1Mb/sec, 16X – 1Mb/sec Automatic wake-up mode for multi-drop applications Start-end break interrupt/status Detects break which originates in the middle of a character On-chip crystal oscillator Power down mode Receiver time-out mode Single +3.3V or +5V power supply Powers up to emulate SC26C92
Philips Semiconductors Product specification
SC28L923.3V–5.0V Dual Universal Asynchronous
Receiver/Transmitter (DUART)
ORDERING INFORMATION
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Philips Semiconductors Product specification
SC28L923.3V–5.0V Dual Universal Asynchronous
Receiver/Transmitter (DUART)
PIN CONFIGURATION DIAGRAM
80XXX PIN CONFIGURATION
Philips Semiconductors Product specification
SC28L923.3V–5.0V Dual Universal Asynchronous
Receiver/Transmitter (DUART)
PIN CONFIGURATION DIAGRAM
68XXX PIN CONFIGURATION
Philips Semiconductors Product specification
SC28L923.3V–5.0V Dual Universal Asynchronous
Receiver/Transmitter (DUART)
Figure 1. Block Diagram (80XXX mode)
Philips Semiconductors Product specification
SC28L923.3V–5.0V Dual Universal Asynchronous
Receiver/Transmitter (DUART)
Figure 2. Block Diagram (68XXX mode)
Philips Semiconductors Product specification
SC28L923.3V–5.0V Dual Universal Asynchronous
Receiver/Transmitter (DUART)
PIN CONFIGURATION FOR 80XXX BUS INTERFACE (INTEL)
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Philips Semiconductors Product specification
SC28L923.3V–5.0V Dual Universal Asynchronous
Receiver/Transmitter (DUART)
PIN CONFIGURATION FOR 68XXX BUS INTERFACE (MOTOROLA)
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Philips Semiconductors Product specification
SC28L923.3V–5.0V Dual Universal Asynchronous
Receiver/Transmitter (DUART)
ABSOLUTE MAXIMUM RATINGS1
NOTES: Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other condition above those indicated in the operation section of this specification is not
implied. For operating at elevated temperatures, the device must be derated based on +150°C maximum junction temperature. This product includes circuitry specifically designed for the protection of its internal devices from damaging effects of excessive static
charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying any voltages larger than the rated maxima. Parameters are valid over specified temperature and voltage range.
DC ELECTRICAL CHARACTERISTICS1, 2, 3
VCC = 5V ± 10%, Tamb = –40°C to +85°C, unless otherwise specified.
NOTES: Parameters are valid over specified temperature and voltage range. All voltage measurements are referenced to ground (GND). For testing, all inputs swing between 0.4V and 3.0V with a transition time of
5ns maximum. For X1/CLK, this swing is between 0.4V and 0.8*VCC. All time measurements are referenced at input voltages of 0.8V and
2.0V and output voltages of 0.8V and 2.0V, as appropriate. Typical values are at +25°C, typical supply voltages, and typical processing parameters. Test conditions for outputs: CL = 125pF, except open drain outputs. Test conditions for open drain outputs: CL = 125pF,
Philips Semiconductors Product specification
SC28L923.3V–5.0V Dual Universal Asynchronous
Receiver/Transmitter (DUART)
DC ELECTRICAL CHARACTERISTICS1, 2, 3
VCC = 3.3V ± 10%, Tamb = –40°C to +85°C, unless otherwise specified.
NOTES: Parameters are valid over specified temperature and voltage range. All voltage measurements are referenced to ground (GND). For testing, all inputs swing between 0.4V and 3.0V with a transition time of
5ns maximum. For X1/CLK, this swing is between 0.4V and 0.8*VCC. All time measurements are referenced at input voltages of 0.8V and
2.0V and output voltages of 0.8V and 2.0V, as appropriate. Typical values are at +25°C, typical supply voltages, and typical processing parameters. Test conditions for outputs: CL = 125pF, except open drain outputs. Test conditions for open drain outputs: CL = 125pF,
constant current source = 2.6mA. Input port pins have active pull-up transistors that will source a typical 2μA from VCC when the input pins are at VSS.
Input port pins at VCC source 0.0μA. All outputs are disconnected. Inputs are switching between CMOS levels of VCC –0.2V and VSS+0.2V.
Philips Semiconductors Product specification
SC28L923.3V–5.0V Dual Universal Asynchronous
Receiver/Transmitter (DUART)
AC CHARACTERISTICS (5 VOLT) 1, 2, 3
VCC = 5.0V ± 10%, Tamb = –40°C to +85°C, unless otherwise specified.
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Philips Semiconductors Product specification
SC28L923.3V–5.0V Dual Universal Asynchronous
Receiver/Transmitter (DUART)
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NOTES: Parameters are valid over specified temperature and voltage range. All voltage measurements are referenced to ground (GND). For testing, all inputs swing between 0.4 V and 3.0 V with a transition time of
5 ns maximum. For X1/CLK this swing is between 0.4 V and 0.8*VCC. All time measurements are referenced at input voltages of 0.8 V and
2.0 V and output voltages of 0.8 V and 2.0 V, as appropriate. Test conditions for outputs: CL = 125 pF, except open drain outputs. Test conditions for open drain outputs: CL = 125 pF,
constant current source = 2.6mA. Typical values are the average values at +25°C and 5V. Timing is illustrated and referenced to the WRN and RDN Inputs. Also, CEN may be the “strobing” input. CEN and RDN (also CEN and
WRN) are ORed internally. The signal asserted last initiates the cycle and the signal negated first terminates the cycle. Guaranteed by characterization of sample units. If CEN is used as the “strobing” input, the parameter defines the minimum High times between one CEN and the next. The RDN signal must
be negated for tRWD to guarantee that any status register changes are valid. Minimum frequencies are not tested but are guaranteed by design. Clocks for 1X mode should maintain a 60/40 duty cycle or better.
10. Minimum DACKN time is tDCR = tDSC + tDCR + two positive edges of the X1 clock. For faster bus cycles, the 80XXX bus timing may be used
while in the 68XXX mode. It is not necessary to wait for DACKN to insure the proper operation of the SC28C92. In all cases the data will be
written to the SC28L92 on the falling edge of DACKN or the rise of CEN. The fall of CEN initializes the bus cycle. The rise of CEN ends the
bus cycle. DACKN low or CEN high completes the write cycle.
NOTES:
Bus cycle times:
(80XXX mode): tDD + tRWD = 70ns @ 5V, 40ns @ 3.3V + rise and fall time of control signals
Philips Semiconductors Product specification
SC28L923.3V–5.0V Dual Universal Asynchronous
Receiver/Transmitter (DUART)
AC CHARACTERISTICS (3.3 VOLT) 1, 2, 3
VCC = 3.3V ± 10%, Tamb = –40°C to +85°C, unless otherwise specified.
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Philips Semiconductors Product specification
SC28L923.3V–5.0V Dual Universal Asynchronous
Receiver/Transmitter (DUART)
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NOTES: Parameters are valid over specified temperature and voltage range. All voltage measurements are referenced to ground (GND). For testing, all inputs swing between 0.4 V and 3.0 V with a transition time of
5 ns maximum. For X1/CLK this swing is between 0.4 V and 0.8*VCC. All time measurements are referenced at input voltages of 0.8 V and
2.0 V and output voltages of 0.8 V and 2.0 V, as appropriate. Test conditions for outputs: CL = 125 pF, except open drain outputs. Test conditions for open drain outputs: CL = 125 pF,
constant current source = 2.6mA. Typical values are the average values at +25°C and 3.3V. Timing is illustrated and referenced to the WRN and RDN Inputs. Also, CEN may be the “strobing” input. CEN and RDN (also CEN and
WRN) are ORed internally. The signal asserted last initiates the cycle and the signal negated first terminates the cycle. Guaranteed by characterization of sample units. If CEN is used as the “strobing” input, the parameter defines the minimum High times between one CEN and the next. The RDN signal must
be negated for tRWD to guarantee that any status register changes are valid. Minimum frequencies are not tested but are guaranteed by design. Clocks for 1X mode should maintain a 60/40 duty cycle or better.
10. Minimum DACKN time is tDCR = tDSC + tDCR + two positive edges of the X1 clock. For faster bus cycles, the 80XXX bus timing may be used
while in the 68XXX mode. It is not necessary to wait for DACKN to insure the proper operation of the SC28C92. In all cases the data will be
written to the SC28L92 on the falling edge of DACKN or the rise of CEN. The fall of CEN initializes the bus cycle. The rise of CEN ends the
bus cycle. DACKN low or CEN high completes the write cycle.
Philips Semiconductors Product specification
SC28L923.3V–5.0V Dual Universal Asynchronous
Receiver/Transmitter (DUART)
Block Diagram
The SC28L92 DUART consists of the following eight major sections:
data bus buffer, operation control, interrupt control, timing,
communications Channels A and B, input port and output port. Refer
to the Block Diagram.
Data Bus Buffer
The data bus buffer provides the interface between the external and
internal data buses. It is controlled by the operation control block to
allow read and write operations to take place between the controlling
CPU and the DUART.
Operation Control
The operation control logic receives operation commands from the
CPU and generates appropriate signals to internal sections to
control device operation. It contains address decoding and read and
write circuits to permit communications with the microprocessor via
the data bus.
Interrupt Control
A single active-Low interrupt output (INTRN) is provided which is
activated upon the occurrence of any of eight internal events.
Associated with the interrupt system are the Interrupt Mask Register
(IMR) and the Interrupt Status Register (ISR). The IMR can be
programmed to select only certain conditions to cause INTRN to be
asserted. The ISR can be read by the CPU to determine all currently
active interrupting conditions. Outputs OP3–OP7 can be
programmed to provide discrete interrupt outputs for the transmitter,
receivers, and counter/timer. When OP3 to OP7 are programmed as
interrupts, their output buffers are changed to the open drain active
low configuration. The OP pins may be used for DMA and modem
control as well. (See output port notes).
FIFO Configuration
Each receiver and transmitter has a 16 byte FIFO. These FIFOs
may be configured to operate at a fill capacity of either 8 or 16 bytes.
This feature may be used if it is desired to operate the 28L92 in strict
compliance with the 26C92. The 8 byte/16 byte mode is controlled
by the MR0[3] bit. A 0 value for this bit sets the 8 bit mode ( the
default); a 1 sets the 16 byte mode.
The FIFO fill interrupt level automatically follow the programming of
the MR0[3] bit. See Tables 3 and 4.
68XXX mode
When the I/M pin is connected to VCC (ground), the operation of the
SC28L92 switches to the bus interface compatible with the Motorola
bus interfaces. Several of the pins change their function as follows:
Ip6 becomes IACKN input
RDN becomes DACKN
WRN becomes R/WN
The interrupt vector is enabled and the interrupt vector will be placed
on the data bus when IACKN is asserted low. The interrupt vector
register is located at address 0xC. The contents of this register are
set to 0x0F on the application of RESETN.
The generation of DACKN uses two positive edges of the X1 clock
as the DACKN delay from the falling edge of CEN. If the CEN is
withdrawn before two edges of the X1 clock occur, the
generation of DACKN is terminated. Systems not strictly requiring
TIMING CIRCUITS
Crystal Clock
The timing block consists of a crystal oscillator, a baud rate
generator, a programmable 16-bit counter/timer, and four clock
selectors. The crystal oscillator operates directly from a crystal
connected across the X1/CLK and X2 inputs. If an external clock of
the appropriate frequency is available, it may be connected to
X1/CLK. The clock serves as the basic timing reference for the Baud
Rate Generator (BRG), the counter/timer, and other internal circuits.
A clock signal within the limits specified in the specifications section
of this data sheet must always be supplied to the DUART. If an
external clock is used instead of a crystal, X1 should be driven using
a configuration similar to the one in Figure 11. Nominal crystal rate is
3.6864 MHz. Rates up to 8 MHz may be used.
BRG
The baud rate generator operates from the oscillator or external
clock input and is capable of generating 28 commonly used data
communications baud rates ranging from 50 to 38.4K baud.
Programming bit 0 of MR0 to a “1” gives additional baud rates of
57.6kB, 115.2kB and 230.4kB (531kHz with X1 at 8.5MHz). These
will be in the 16X mode. A 3.6864 MHz crystal or external clock
must be used to get the standard baud rates. The clock outputs from
the BRG are at 16X the actual baud rate. The counter/timer can be
used as a timer to produce a 16X clock for any other baud rate by
counting down the crystal clock or an external clock. The four clock
selectors allow the independent selection, for each receiver and
transmitter, of any of these baud rates or external timing signal.
Counter/Timer
The counter timer is a 16–bit programmable divider that operates in
one of three modes: counter, timer, time out. In the timer mode it
generates a square wave. In the counter mode it generates a time
delay. In the time out mode it monitors the time between received
characters. The C/T uses the numbers loaded into the
Counter/Timer Lower Register (CTLR) and the Counter/Timer Upper
Register (CTUR) as its divisor.
The counter/timer clock source and mode of operation (counter or
timer) is selected by the Auxiliary Control Register bits 6 to 4
(ACR[6:4]). The output of the counter/timer may be used for a baud
rate and/or may be output to the OP pins for some external function
that may be totally unrelated to data transmission. The
counter/timer also sets the counter/timer ready bit in the Interrupt
Status Register (ISR) when its output transitions from 1 to 0. A
register read address (see Table 1) is reserved to issue a start
counter/timer command and a second register read address is
reserved to issue a stop command. The value of D(7:0) is ignored.
The START command always loads the contents of CTUR, CTLR to
the counting registers. The STOP command always resets the ISR
(3) bit in the interrupt status register.
Timer Mode
In the timer mode a symmetrical square wave is generated whose
half period is equal in time to division of the selected counter/timer
clock frequency by the 16–bit number loaded in the CTLR CTUR.
Thus, the frequency of the counter/timer output will be equal to the
counter/timer clock frequency divided by twice the value of the
CTUR CTLR. While in the timer mode the ISR bit 3 (ISR[3]) will be
set each time the counter/timer transitions from 1 to 0. (High to low)
Philips Semiconductors Product specification
SC28L923.3V–5.0V Dual Universal Asynchronous
Receiver/Transmitter (DUART)
This continues regardless of issuance of the stop counter command.
ISR[3] is reset by the stop counter command.
NOTE: Reading of the CTU and CTL registers in the timer mode is
not meaningful. When the C/T is used to generate a baud rate and
the C/T is selected through the CSR then the receivers and/or
transmitter will be operating in the 16x mode. Calculation for the
number ‘n’ to program the counter timer upper and lower registers is
shown below. N=2 x 16 x Baud rate desired/(C/T Clock Frequency
Often this division will result in a non–integer number; 26.3 for
example. One can only program integer numbers to a digital divider.
Therefore 26 would be chosen. This gives a baud rate error of
0.3/26.3 which is 1.14%; well within the ability of the asynchronous
mode of operation.
Counter Mode
In the counter mode the counter/timer counts the value of the CTLR
CTUR down to zero and then sets the ISR[3] bit and sets the
counter/timer output from 1 to 0. It then rolls over to 65,365 and
continues counting with no further observable effect. Reading the
C/T in the counter mode outputs the present state of the C/T. If the
C/T is not stopped, a read of the C/T may result in changing data on
the data bus.
Timeout Mode
The timeout mode uses the received data stream to control the
counter. The time–out mode forces the C/T into the timer mode.
Each time a received character is transferred from the shift register
to the RxFIFO, the counter is restarted. If a new character is not
received before the counter reaches zero count, the counter ready
bit is set, and an interrupt can be generated. This mode can be
used to indicate when data has been left in the Rx FIFO for more
than the programmed time limit. If the receiver has been
programmed to interrupt the CPU when the receive FIFO is full, and
the message ends before the FIFO is full, the CPU will not be
interrupted for the remaining characters in the RxFIFO.
By programming the C/T such that it would time out in just over one
character time, the above situation could be avoided. The
processor would be interrupted any time the data stream had
stopped for more than one character time. NOTE: This is very
similar to the watch dog time of MR0. The difference is in the
programmability of the delay time and that the watchdog timer is
restarted by either a receiver load to the RxFIFO or a system read
from it.
This mode is enabled by writing the appropriate command to the
command register. Writing an ‘Ax’ to CRA or CRB will invoke the
timeout mode for that channel. Writing a ‘Cx’ to CRA or CRB will
disable the timeout mode. Only one receiver should use this mode
at a time. However, if both are on, the timeout occurs after both
receivers have been inactive for the timeout period. The start of the
C/T will be on the logical or of the two receivers.
The timeout mode disables the regular START/STOP counter
commands and puts the C/T into counter mode under the control of
the received data stream. Each time a received character is
transferred from the shift register to the RxFIFO, the C/T is stopped
after one C/T clock, reloaded with the value in CTUR and CTLR and
then restarted on the next C/T clock. If the C/T is allowed to end the
count before a new character has been received, the counter ready
Bit, ISR[3], will be set. If IMR [3] is set, this will generate an
the counter until the next character is received. The counter timer is
controlled with six commands: Start/Stop C/T, Read/Write
Counter/Timer lower register and Read/Write Counter/Timer upper
register. These commands have slight differences depending on the
mode of operation. Please see the detail of the commands under
the CTLR CTUR Register descriptions.
Time Out Mode Caution
When operating in the special time out mode, it is possible to
generate what appears to be a “false interrupt”, i.e., an interrupt
without a cause. This may result when a time–out interrupt occurs
and then, BEFORE the interrupt is serviced, another character is
received, i.e., the data stream has started again. (The interrupt
latency is longer than the pause in the data stream.) In this case,
when a new character has been receiver, the counter/timer will be
restarted by the receiver, thereby withdrawing its interrupt. If, at this
time, the interrupt service begins for the previously seen interrupt, a
read of the ISR will show the “Counter Ready” bit not set. If nothing
else is interrupting, this read of the ISR will return a x’00 character.
This action may present the appearance of a spurious interrupt.
Communications Channels A and B
Each communications channel of the SC28L92 comprises a
full-duplex asynchronous receiver/transmitter (UART). The operating
frequency for each receiver and transmitter can be selected
independently from the baud rate generator, the counter/timer, or
from an external input. The transmitter accepts parallel data from the
CPU, converts it to a serial bit stream, inserts the appropriate start,
stop, and optional parity bits and outputs a composite serial stream
of data on the TxD output pin. The receiver accepts serial data on
the RxD pin, converts this serial input to parallel format, checks for
start bit, stop bit, parity bit (if any), or break condition and sends an
assembled character to the CPU via the receive FIFO. Three status
bits (Break Received, Framing and Parity Errors) are also FIFOed
with each data character.
Input Port
The inputs to this unlatched 7-bit (6-bit for 68xxx mode) port can be
read by the CPU by performing a read operation at address H’D’. A
High input results in a logic 1 while a Low input results in a logic 0.
D7 will always read as a logic 1. The pins of this port can also serve
as auxiliary inputs to certain portions of the DUART logic, modem
and DMA.
Four change-of-state detectors are provided which are associated
with inputs IP3, IP2, IP1 and IP0. A High-to-Low or Low-to-High
transition of these inputs, lasting longer than 25–50 μs, will set the
corresponding bit in the input port change register. The bits are
cleared when the register is read by the CPU. Any change-of-state
can also be programmed to generate an interrupt to the CPU.
The input port change of state detection circuitry uses a 38.4 kHz
sampling clock derived from one of the baud rate generator taps. This
results in a sampling period of slightly more than 25 μs (this assumes
that the clock input is 3.6864 MHz). The detection circuitry, in order to
guarantee that a true change in level has occurred, requires two
successive samples at the new logic level be observed. As a
consequence, the minimum duration of the signal change is 25 μs if
the transition occurs “coincident with the first sample pulse”. The
50 μs time refers to the situation in which the change-of-state is “just
missed” and the first change-of-state is not detected until 25 μs later.
Philips Semiconductors Product specification
SC28L923.3V–5.0V Dual Universal Asynchronous
Receiver/Transmitter (DUART)
controls the source of the data for the output ports OP2 through
OP7. The data source for output ports OP0 and OP1 is controlled by
the MR and CR registers. When the OPR is the source of the data
for the output ports, the data at the ports is inverted from that in the
OPR register. The content of the OPR register is controlled by the
“Set Output Port Bits Command” and the “Reset Output Bits
Command”. These commands are at E and F, respectively. When
these commands are used, action takes place only at the bit
locations where ones exist. For example, a one in bit location 5 of
the data word used with the “Set Output Port bits” command will
result in OPR5 being set to one. The OP5 would then be set to zero
(VSS). Similarly, a one in bit position 5 of the data word associated
with the “Reset Output Ports Bits” command would set OPR5 to
zero and, hence, the pin OP5 to a one (VDD).
These pins along with the IP pins and their change of state detectors
are often used for modem and DMA control.
OPERATION
Transmitter
The SC28L92 is conditioned to transmit data when the transmitter is
enabled through the command register. The SC28L92 indicates to
the CPU that it is ready to accept a character by setting the TxRDY
bit in the status register. This condition can be programmed to
generate an interrupt request at OP6 or OP7 and INTRN. When the
transmitter is initially enabled the TxRDY and TxEMPT bits will be
set in the status register. When a character is loaded to the transmit
FIFO the TxEMPT bit will be reset. The TxEMPT will not set until: 1)
the transmit FIFO is empty and the transmit shift register has
finished transmitting the stop bit of the last character written to the
transmit FIFO, or 2) the transmitter is disabled and then re-enabled.
The TxRDY bit is set whenever the transmitter is enabled and the
TxFIFO is not full. Data is transferred from the holding register to
transmit shift register when it is idle or has completed transmission
of the previous character. Characters cannot be loaded into the
TxFIFO while the transmitter is disabled.
The transmitter converts the parallel data from the CPU to a serial
bit stream on the TxD output pin. It automatically sends a start bit
followed by the programmed number of data bits, an optional parity
bit, and the programmed number of stop bits. The least significant
bit is sent first. Following the transmission of the stop bits, if a new
character is not available in the TxFIFO, the TxD output remains
High and the TxEMT bit in the Status Register (SR) will be set to 1.
Transmission resumes and the TxEMT bit is cleared when the CPU
loads a new character into the TxFIFO.
If the transmitter is disabled it continues operating until the character
currently being transmitted and any characters in the TxFIFO,
including parity and stop bits, have been transmitted. New data
cannot be loaded to the TxFIFO when the transmitter is disabled.
When the transmitter is reset it stops sending data immediately.
The transmitter can be forced to send a break (a continuous low
condition) by issuing a START BREAK command via the CR
register. The break is terminated by a STOP BREAK command or a
transmitter reset.
If CTS option is enabled (MR2[4] = 1), the CTS input at IP0 or IP1
must be Low in order for the character to be transmitted. The
has returned to the low state. CTS going high during the serialization
of a character will not affect that character.
The transmitter can also control the RTSN outputs, OP0 or OP1 via
MR2[5]. When this mode of operation is set, the meaning of the OP0
or OP1 signals will usually be ‘end of message’. See description of
the MR2[5] bit for more detail. This feature may be used to
automatically “turn around” a transceiver in simplex systems.
Receiver
The SC28L92 is conditioned to receive data when enabled through
the command register. The receiver looks for a High-to-Low
(mark-to-space) transition of the start bit on the RxD input pin. If a
transition is detected, the state of the RxD pin is sampled each 16X
clock for 7-1/2 clocks (16X clock mode) or at the next rising edge of
the bit time clock (1X clock mode). If RxD is sampled High, the start
bit is invalid and the search for a valid start bit begins again. If RxD
is still Low, a valid start bit is assumed and the receiver continues to
sample the input at one bit time intervals at the theoretical center of
the bit, until the proper number of data bits and parity bit (if any)
have been assembled, and one stop bit has been detected. The
least significant bit is received first. The data is then transferred to
the Receive FIFO and the RxRDY bit in the SR is set to a 1. This
condition can be programmed to generate an interrupt at OP4 or
OP5 and INTRN. If the character length is less than 8 bits, the most
significant unused bits in the RxFIFO are set to zero.
After the stop bit is detected, the receiver will immediately look for
the next start bit. However, if a non-zero character was received
without a stop bit (framing error) and RxD remains Low for one half
of the bit period after the stop bit was sampled, then the receiver
operates as if a new start bit transition had been detected at that
point (one-half bit time after the stop bit was sampled).
The parity error, framing error, and overrun error (if any) are strobed
into the SR from the next byte to be read from the Rx FIFO. If a
break condition is detected (RxD is Low for the entire character
including the stop bit), a character consisting of all zeros will be
loaded into the RxFIFO and the received break bit in the SR is set to
1. The RxD input must return to high for two (2) clock edges of the
X1 crystal clock for the receiver to recognize the end of the break
condition and begin the search for a start bit.
This will usually require a high time of one X1 clock period or 3
X1 edges since the clock of the controller is not synchronous
to the X1 clock.
Transmitter Reset and Disable
Note the difference between transmitter disable and reset. A
transmitter reset stops transmitter action immediately, clears the
transmitter FIFO and returns the idle state. A transmitter disable
withdraws the transmitter interrupts but allows the transmitter to
continue operation until all bytes in its FIFO and shift register have
been transmitted including the final stop bits. It then returns to its
idle state.
Receiver FIFO
The RxFIFO consists of a First-In-First-Out (FIFO) stack with a
capacity of 8 or 16 characters. Data is loaded from the receive shift
register into the topmost empty position of the FIFO. The RxRDY bit
in the status register is set whenever one or more characters are
available to be read, and a FFULL status bit is set if all 8 or 16 stack
Philips Semiconductors Product specification
SC28L923.3V–5.0V Dual Universal Asynchronous
Receiver/Transmitter (DUART)
status bits (see below) are ‘popped’ thus emptying a FIFO position
for new data.
A disabled receiver with data in its FIFO may generate an interrupt
(see “Receiver Status Bits”, below). Its status bits remain active and
its watchdog, if enabled, will continue to operate.
Receiver Status Bits
In addition to the data word, three status bits (parity error, framing
error, and received break) are also appended to each data character
in the FIFO. The overrun error, MR1(5), is not FIFOed.
Status can be provided in two ways, as programmed by the error
mode control bit in the mode register. In the ‘character’ mode, status
is provided on a character-by-character basis; the status applies
only to the character at the top of the FIFO. In the ‘block’ mode, the
status provided in the SR for these three bits is the logical-OR of the
status for all characters coming to the top of the FIFO since the last
‘reset error’ from the command register was issued. In either mode
reading the SR does not affect the FIFO. The FIFO is ‘popped’ only
when the RxFIFO is read. Therefore the status register should be
read prior to reading the FIFO.
If the FIFO is full when a new character is received, that character is
held in the receive shift register until a FIFO position is available. If
an additional character is received while this state exits, the
contents of the FIFO are not affected; the character previously in the
shift register is lost and the overrun error status bit (SR[4]) will be
set-upon receipt of the start bit of the new (overrunning) character.
The receiver can control the deactivation of RTS. If programmed to
operate in this mode, the RTSN output will be negated when a valid
start bit was received and the FIFO is full. When a FIFO position
becomes available, the RTSN output will be re-asserted (set low)
automatically. This feature can be used to prevent an overrun, in the
receiver, by connecting the RTSN output to the CTSN input of the
transmitting device.
If the receiver is disabled, the FIFO characters can be read.
However, no additional characters can be received until the receiver
is enabled again. If the receiver is reset, the FIFO and all of the
receiver status, and the corresponding output ports and interrupt are
reset. No additional characters can be received until the receiver is
enabled again.
Receiver Reset and Disable
Receiver disable stops the receiver immediately—data being
assembled in the receiver shift register is lost. Data and status in the
FIFO is preserved and may be read. A re-enable of the receiver
after a disable will cause the receiver to begin assembling
characters at the next start bit detected.
A receiver reset will discard the present shift register date, reset the
receiver ready bit (RxRDY), clear the status of the byte at the top of
the FIFO and re-align the FIFO read/write pointers.
Watchdog
A ‘watchdog timer’ is associated with each receiver. Its interrupt is
enabled by MR0[7]. The purpose of this timer is to alert the control
processor that characters are in the RxFIFO which have not been
read. This situation may occur at the end of a transmission when the
last few characters received are not sufficient to cause an interrupt.
Receiver Time-out Mode
In addition to the watch dog timer described in the receiver section,
the counter/timer may be used for a similar function. Its
programmability, of course, allows much greater precision of time
out intervals.
The time-out mode uses the received data stream to control the
counter. Each time a received character is transferred from the shift
register to the RxFIFO, the counter is restarted. If a new character is
not received before the counter reaches zero count, the counter
ready bit is set, and an interrupt can be generated. This mode can
be used to indicate when data has been left in the RxFIFO for more
than the programmed time limit. Otherwise, if the receiver has been
programmed to interrupt the CPU when the receive FIFO is full, and
the message ends before the FIFO is full, the CPU may not know
there is data left in the FIFO. The CTU and CTL value would be
programmed for just over one character time, so that the CPU would
be interrupted as soon as it has stopped receiving continuous data.
This mode can also be used to indicate when the serial line has
been marking for longer than the programmed time limit. In this
case, the CPU has read all of the characters from the FIFO, but the
last character received has started the count. If there is no new data
during the programmed time interval, the counter ready bit will get
set, and an interrupt can be generated.
The time-out mode is enabled by writing the appropriate command
to the command register. Writing an ‘Ax’ to CRA or CRB will invoke
the time-out mode for that channel. Writing a ‘Cx’ to CRA or CRB
will disable the time-out mode. The time-out mode should only be
used by one channel at once, since it uses the C/T. If, however, the
time-out mode is enabled from both receivers, the time-out will occur
only when both receivers have stopped receiving data for the
time-out period. CTU and CTL must be loaded with a value greater
than the normal receive character period. The time-out mode
disables the regular START/STOP Counter commands and puts the
ca/T into counter mode under the control of the received data
stream. Each time a received character is transferred from the shift
register to the RxFIFO, the C/T is stopped after 1 C/T clock,
reloaded with the value in CTU and CTL and then restarted on the
next C/T clock. If the C/T is allowed to end the count before a new
character has been received, the counter ready bit, ISR[3], will be
set. If IMR[3] is set, this will generate an interrupt. Receiving a
character after the C/T has timed out will clear the counter ready bit,
ISR[3], and the interrupt. Invoking the ‘Set Time-out Mode On’
command, CRx = ‘Ax’, will also clear the counter ready bit and stop
the counter until the next character is received.
Time Out Mode Caution
When operating in the special time out mode, it is possible to
generate what appears to be a “false interrupt”, i.e., an interrupt
without a cause. This may result when a time-out interrupt occurs
and then, BEFORE the interrupt is serviced, another character is
received, i.e., the data stream has started again. (The interrupt
latency is longer than the pause in the data stream.) In this case,
when a new character has been receiver, the counter/timer will be
restarted by the receiver, thereby withdrawing its interrupt. If, at this
time, the interrupt service begins for the previously seen interrupt, a
read of the ISR will show the “Counter Ready” bit not set. If nothing
else is interrupting, this read of the ISR will return a x’00 character.
Multi-drop Mode (9-bit or Wake-Up)
Philips Semiconductors Product specification
SC28L923.3V–5.0V Dual Universal Asynchronous
Receiver/Transmitter (DUART)
MR1A[4:3]or MR1B[4:3] to ‘11’ for Channels A and B, respectively.
In this mode of operation, a ‘master’ station transmits an address
character followed by data characters for the addressed ‘slave’
station. The slave stations, with receivers that are normally disabled,
examine the received data stream and ‘wakeup’ the CPU (by setting
RxRDY)only upon receipt of an address character. The CPU
compares the received address to its station address and enables
the receiver if it wishes to receive the subsequent data characters.
Upon receipt of another address character, the CPU may disable the
receiver to initiate the process again.
A transmitted character consists of a start bit, the programmed
number of data bits, and Address/Data (A/D) bit, and the
programmed number of stop bits. The polarity of the transmitted A/D
bit is selected by the CPU by programming bit MR1A[2]/MR1B[2].
MR1A[2]/MR1B[2] = 0 transmits a zero in the A/D bit position, which
identifies the corresponding data bits as data while
MR1A[2]/MR1B[2] = 1 transmits a one in the A/D bit position, which
identifies the corresponding data bits as an address. The CPU
should program the mode register prior to loading the corresponding
data bits into the TxFIFO.
In this mode, the receiver continuously looks at the received data
stream, whether it is enabled or disabled. If disabled, it sets the
RxRDY status bit and loads the character into the RxFIFO if the
received A/D bit is a one (address tag), but discards the received
character if the received A/D bit is a zero (data tag). If enabled, all
received characters are transferred to the CPU via the RxFIFO. In
either case, the data bits are loaded into the data FIFO while the
A/D bit is loaded into the status FIFO position normally used for
parity error (SRA[5] or SRB[5]). Framing error, overrun error, and
break detect operate normally whether or not the receive is enabled.
PROGRAMMING
The operation of the DUART is programmed by writing control words
into the appropriate registers. Operational feedback is provided via
status registers which can be read by the CPU. The addressing of
the registers is described in Table 1.
The contents of certain control registers are initialized to zero on
RESET. Care should be exercised if the contents of a register are
changed during operation, since certain changes may cause
operational problems.
For example, changing the number of bits per character while the
transmitter is active may cause the transmission of an incorrect
character. In general, the contents of the MR, the CSR, and the
OPCR should only be changed while the receiver(s) and
transmitter(s) are not enabled, and certain changes to the ACR
should only be made while the C/T is stopped.
Each channel has 3 mode registers (MR0, 1, 2) which control the
basic configuration of the channel. Access to these registers is
controlled by independent MR address pointers. These pointers are
set to 0 or 1 by MR control commands in the command register
“Miscellaneous Commands”. Each time the MR registers are
accessed the MR pointer increments, stopping at MR2. It remains
pointing to MR2 until set to 0 or 1 via the miscellaneous commands
of the command register. The pointer is set to 1 on reset for
compatibility with previous Philips Semiconductors UART software.
Mode, command, clock select, and status registers are duplicated
for each channel to provide total independent operation and control.
Refer to Table 2 for register bit descriptions. The reserved registers
at addresses H‘02’ and H‘0A’ should never be read during normal
operation since they are reserved for internal diagnostics.
Table 1. SC28L92 register addressing READ (RDN = 0), WRITE (WRN = 0)
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NOTE: The three MR registers are accessed via the MR Pointer and Commands 0x1n and 0xBn (where n = represents receiver and transmitter enable bits)
Philips Semiconductors Product specification
SC28L923.3V–5.0V Dual Universal Asynchronous
Receiver/Transmitter (DUART)
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Table 2. Condensed Register bit formats
MR0 – MODE REGISTER 0
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MR1 – MODE REGISTER 1
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MR2 – MODE REGISTER 2
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CSR – CLOCK SELECT REGISTER
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CR –COMMAND REGISTER
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SR – CHANNEL STATUS REGISTER
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IMR – INTERRUPT MASK REGISTER (ENABLES INTERRUPTS)
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ISR – INTERRUPT STATUS REGISTER
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CTPU – COUNTER TIMER PRESET REGISTERS, UPPER
Philips Semiconductors Product specification
SC28L923.3V–5.0V Dual Universal Asynchronous
Receiver/Transmitter (DUART)
CTPL – COUNTER TIMER PRESET REGISTER, LOWER
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ACR – AUXILIARY CONTROL REGISTER AND CHANGE OF STATE CONTROL
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IPCR – INPUT PORT CHANGE REGISTER
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IPR – INPUT PORT REGISTER
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SOPR – SET THE OUTPUT PORT BITS (OPR)
ROPR – RESET OUTPUT PORT BITS (OPR)
OPCR OUTPUT PORT CONFIGURATION REGISTER (NOTE OP1 AND OP0 ARE THE RTSN OUTPUT AND
ARE CONTROLLED BY THE MR REGISTER)
REGISTER DESCRIPTIONS Mode Registers
MR0A Mode Register 0. MR0 is accessed by setting the MR pointer to 0 via the command register command B.
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MR0[7]—This bit controls the receiver watch dog timer. 0 = disable,
1 = enable. When enabled, the watch dog timer will generate a
receiver interrupt if the receiver FIFO has not been accessed within
64 bit times of the receiver 1X clock. This is used to alert the control
processor that data is in the RxFIFO that has not been read. This
situation may occur when the byte count of the last part of a
message is not large enough to generate an interrupt.
MR0[6]—Bit 2 of receiver FIFO interrupt level. This bit along with Bit
6 of MR1 sets the fill level of the FIFO that generates the receiver
interrupt.
MR0[6] MR1[6] Note that this control is split between MR0 and
MR1. This is for backward compatibility to the SC2692 and
SCN2681.
Table 3. Receiver FIFO interrupt fill level
(MR0(3) = 0 (8 bytes)
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Table 3a. Receiver FIFO interrupt fill
level(MR0(3)=1 (16 bytes)
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Partno	Mfg	Dc	Qty	Available	Descript
SC28L92A1A	PH	N/a	8	avai	3.3V-5.0V Dual Universal Asynchronous Receiver/Transmitter (DUART)
SC28L92A1A	PHILIPS	N/a	22	avai	3.3V-5.0V Dual Universal Asynchronous Receiver/Transmitter (DUART)
SC28L92A1B	PH	N/a	41	avai	3.3V-5.0V Dual Universal Asynchronous Receiver/Transmitter (DUART)