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SC18IS602BIPW
I2C-bus to SPI bridge
1. General descriptionThe SC18IS602B is designed to serve as an interface between a standard I2 C-bus of a
microcontroller and an SPI bus. This allows the microcontroller to communicate directly
with SPI devices through its I2 C-bus. The SC18IS602B operates as an I2 C-bus
slave-transmitter or slave-receiver and an SPI master. The SC18IS602B controls all the
SPI bus-specific sequences, protocol, and timing. The SC18IS602B has its own internal
oscillator, and it supports four SPI chip select outputs that may be configured as GPIO
when not used.
2. Features and benefitsI2 C-bus slave interface operating up to 400 kHz SPI master operating up to 1.8 Mbit/s 200-byte data buffer Up to four slave select outputs Up to four programmable I/O pins Operating supply voltage: 2.4 V to 3.6V Low power mode Internal oscillator option Active LOW interrupt output ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per
JESD22-A115, and 1000 V CDM per JESD22-C101 Latch-up testing is done to JEDEC Standard JESD78 that exceeds 100 mA Very small 16-pin TSSOP
3. Applications Converting I2 C-bus to SPI Adding additional SPI bus controllers to an existing system
SC18IS602B2 C-bus to SPI bridge
Rev. 5 — 3 August 2010 Product data sheet
NXP Semiconductors SC18IS602B2 C-bus to SPI bridge
4. Ordering information
5. Block diagram
Table 1. Ordering informationSC18IS602BIPW TSSOP16 plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1
NXP Semiconductors SC18IS602B2 C-bus to SPI bridge
6. Pinning information
6.1 Pinning
6.2 Pin description
Table 2. Pin descriptionSS0/GPIO0 1 I/O SPI slave select output 0 (active LOW) or GPIO0
SS1/GPIO1 2 I/O SPI slave select output 1 (active LOW) or GPIO1
RESET 3 I reset input (active LOW)
VSS 4 - ground supply
MISO 5 I Master In, Slave Out
MOSI 6 O Master Out, Slave In
SDA 7 I/O I2 C-bus data
SCL 8 I I2 C-bus clock
INT 9 O interrupt output (active LOW)
SS2/GPIO2 10 I/O SPI slave select output 2 (active LOW) or GPIO2
SPICLK 11 O SPI clock
VDD 12 - supply voltage
SS3/GPIO3 13 I/O SPI slave select output 3 (active LOW) or GPIO3 14 I address input 0 15 I address input 1 16 I address input 2
NXP Semiconductors SC18IS602B2 C-bus to SPI bridge
7. Functional descriptionThe SC18IS602B acts as a bridge between an I2 C-bus and an SPI interface. It allows an 2 C-bus master device to communicate with any SPI-enabled device.
7.1I2 C-bus interfaceThe I2 C-bus uses two wires (SDA and SCL) to transfer information between devices
connected to the bus, and it has the following features:
Bidirectional data transfer between masters and slaves
Multi-master bus (no central master)
Arbitration between simultaneously transmitting masters without corruption of serial
data on the bus
Serial clock synchronization allows devices with different bit rates to communicate via
one serial bus
Serial clock synchronization can be used as a handshake mechanism to suspend and
resume serial transfer
The I2 C-bus may be used for test and diagnostic purposes
A typical I2 C-bus configuration is shown in Figure 3. (Refer to NXP Semiconductors
UM10204, “I2 C-bus specification and user manual”, at
/documents/user_manual/UM10204.pdf.)
The SC18IS602B device provides a byte-oriented I2 C-bus interface that supports data
transfers up to 400 kHz. When the I2 C-bus master is reading data from SC18IS602B, the
device will be a slave-transmitter. The SC18IS602B will be a slave-receiver when the 2 C-bus master is sending data. At no time does the SC18IS602B act as an I2 C-bus
master, however, it does have the ability to hold the SCL line LOW between bytes to
complete its internal processes.
NXP Semiconductors SC18IS602B2 C-bus to SPI bridge
7.1.1 AddressingThe first seven bits of the first byte sent after a START condition defines the slave address
of the device being accessed on the bus. The eighth bit determines the direction of the
message. A ‘0’ in the least significant position of the first byte means that the master will
write information to a selected slave. A ‘1’ in this position means that the master will read
information from the slave. When an address is sent, each device in a system compares
the first seven bits after the START condition with its address. If they match, the device
considers itself addressed by the master as a slave-receiver or slave-transmitter,
depending on the R/W bit.
A slave address of the SC18IS602B is comprised of a fixed and a programmable part.
The programmable part of the slave address enables the maximum possible number of
such devices to be connected to the I2 C-bus. Since the SC18IS602B has three
programmable address bits (defined by the A2, A1, and A0 pins), it is possible to have
eight of these devices on the same bus.
The state of the A2, A1, and A0 pins are latched at reset. Changes made after reset will
not alter the address.
When SC18IS602B is busy after the address byte is transmitted, it will not acknowledge
its address.
7.1.2 Write to data bufferAll communications to or from the SC18IS602B occur through the data buffer. The data
buffer is 200 bytes deep. A message begins with the SC18IS602B address, followed by
the Function ID. Depending upon the Function ID, zero to 200 data bytes can follow.
The SC18IS602B will place the data received into a buffer and continue loading the buffer
until a STOP condition is received. After the STOP condition is detected, further
communications will not be acknowledged until the function designated by the Function ID
has been completed.
7.1.3 SPI read and write - Function ID 01h to 0FhData in the buffer will be sent to the SPI port if the Function ID is 01h to 0Fh. The Function
ID contains the Slave Select (SS) to be used for the transmission on the SPI port. There
are four Slave Selects that can be used, with each SS being selected by one of the bits in
NXP Semiconductors SC18IS602B2 C-bus to SPI bridgethe Function ID. There is no restriction on the number or combination of Slave Selects that
can be enabled for an SPI message. If more than one SSn pin is enabled at one time, the
user should be aware of possible contention on the data outputs of the SPI slave devices.
The data on the SPI port will contain the same information as the I2 C-bus data, but without
the slave address and Function ID. For example, if the message shown in Figure 6 is
transmitted on the I2 C-bus, the SPI bus will send the message shown in Figure7.
The SC18IS602B counts the number of data bytes sent to the I2 C-bus port and will
automatically send this same number of bytes to the SPI bus. As the data is transmitted
from the MOSI pin, it is also read from the MISO pin and saved in the data buffer.
Therefore, the old data in the buffer is overwritten. The data in the buffer can then be read
back.
If the data from the SPI bus needs to be returned to the I2 C-bus master, the process must
be completed by reading the data buffer. Section 8 gives an example of an SPI read.
7.1.4 Read from bufferA read from the data buffer requires no Function ID. The slave address with the R/W bit
set to a ‘1’ will cause the SC18IS602B to send the buffer contents to the I2 C-bus master.
The buffer contents are not modified during the read process.
A typical write and read from an SPI EEPROM is shown in Section8.
Table 3. Function ID 01h to 0Fh0000 SS3 SS2 SS1 SS0
NXP Semiconductors SC18IS602B2 C-bus to SPI bridge
7.1.5 Configure SPI Interface - Function ID F0hThe SPI hardware operating mode, data direction, and frequency can be changed by
sending a ‘Configure SPI Interface’ command to the I2 C-bus.
After the SC18IS602B address is transmitted on the bus, the Configure SPI Interface
Function ID (F0h) is sent followed by a byte which will define the SPI communications.
The Clock Phase bit (CPHA) allows the user to set the edges for sampling and changing
data. The Clock Polarity bit (CPOL) allows the user to set the clock polarity. Figure 19 and
Figure 20 show the different settings of Clock Phase bit CPHA.
Table 4. Configure SPI Interface (F0h) bit allocation
Table 5. Configure SPI Interface (F0h) bit description7:6 - reserved ORDER When logic 0, the MSB of the data word is transmitted first. If logic 1, the LSB of the data word is transmitted first. - reserved
3:2 MODE1:MODE0 Mode selection
00 - SPICLK LOW when idle; data clocked in on leading edge
(CPOL= 0, CPHA=0)
01 - SPICLK LOW when idle; data clocked in on trailing edge (CPOL= 0, CPHA=1)
10 - SPICLK HIGH when idle; data clocked in on trailing edge
(CPOL= 1, CPHA=0)
11 - SPICLK HIGH when idle; data clocked in on leading edge
(CPOL= 1, CPHA=1)
1:0 F1:F0 SPI clock rate
00 - 1843 kHz
01 - 461 kHz
10 - 115 kHz
11 - 58 kHz
NXP Semiconductors SC18IS602B2 C-bus to SPI bridge
7.1.6 Clear Interrupt - Function ID F1hAn interrupt is generated by the SC18IS602B after any SPI transmission has been
completed. This interrupt can be cleared (INT pin HIGH) by sending a ‘Clear Interrupt’
command. It is not necessary to clear the interrupt; when polling the device, this function
may be ignored.
7.1.7 Idle mode - Function ID F2hA low-power mode may be entered by sending the ‘Idle Mode’ command.
The Idle mode will be exited when its I2 C-bus address is detected.
7.1.8 GPIO Write - Function ID F4hThe state of the pins defined as GPIO may be changed using the Port Write function.
The data byte following the F4h command will determine the state of SS3, SS2, SS1, and
SS0, if they are configured as GPIO. The Port Enable function will define if these pins are
used as SPI Slave Selects or if they are GPIO.
Table 6. GPIO Write (F0h) bit allocation
NXP Semiconductors SC18IS602B2 C-bus to SPI bridge
7.1.9 GPIO Read - Function ID F5hThe state of the pins defined as GPIO may be read into the SC18IS602B data buffer using
the GPIO Read function.
Note that this function does not return the value of the GPIO. To receive the GPIO
contents, a one-byte Read Buffer command would be required. The value of the Read
Buffer command will return the following byte.
Data for pins not defined as GPIO are undefined.
A GPIO Read is always performed to update the GPIO data in the buffer. The buffer is
undefined after the GPIO data is read back from the buffer. Therefore, reading data from
the GPIO always requires a two-message sequence (GPIO Read, followed by Read
Buffer).
7.1.10 GPIO Enable - Function ID F6hAt reset, the Slave Select pins (SS0, SS1, SS2 and SS3) are configured to be used as
slave select outputs. If these pins are not required for the SPI functions, they can be used
as GPIO after they are enabled as GPIO. Any combination of pins may be configured to
function as GPIO or Slave Selects.
After the GPIO Enable function is sent, the ports defined as GPIO will be configured as
quasi-bidirectional.
The data byte following the F6h command byte will determine which pins can be used as
GPIO. A logic 1 will enable the pin as a GPIO, while a logic 0 will disable GPIO control.
Table 7. GPIO Read (F5h) bit allocationXXXX SS3 SS2 SS1 SS0
Table 8. GPIO Enable (F6h) bit allocationXXXX SS3 SS2 SS1 SS0
NXP Semiconductors SC18IS602B2 C-bus to SPI bridge
7.1.11 GPIO Configuration - Function ID F7hThe pins defined as GPIO may be configured by software to one of four types on a
pin-by-pin basis. These are: quasi-bidirectional, push-pull, open-drain, and input-only.
Two bits select the output type for each port pin.
The SSn pins defined as GPIO, for example SS0.0 and SS0.1, may be configured by
software to one of four types. These are: quasi-bidirectional, push-pull, open-drain, and
input-only. Two configuration bits in GPIO Configuration register for each pin select the
type for each pin. A pin has Schmitt-triggered input that also has a glitch suppression
circuit.
7.1.11.1 Quasi-bidirectional output configurationQuasi-bidirectional outputs can be used both as an input and output without the need to
reconfigure the pin. This is possible because when the pin outputs a logic HIGH, it is
weakly driven, allowing an external device to pull the pin LOW. When the pin is driven
LOW, it is driven strongly and able to sink a large current. There are three pull-up
transistors in the quasi-bidirectional output that serve different purposes.
One of these pull-ups, called the ‘very weak’ pull-up, is turned on whenever the port latch
for the pin contains a logic 1. This very weak pull-up sources a very small current that will
pull the pin HIGH if it is left floating.
A second pull-up, called the ‘weak’ pull-up, is turned on when the port latch for the pin
contains a logic 1 and the pin itself is also at a logic 1 level. This pull-up provides the
primary source current for a quasi-bidirectional pin that is outputting a 1. If this pin is
Table 9. GPIO Configuration (F7h) bit allocationSS3.1 SS3.0 SS2.1 SS2.0 SS1.1 SS1.0 SS0.1 SS0.0
Table 10. GPIO Configuration (F7h) bit description SS3.1 SS3[1:0] = 00: quasi-bidirectional
SS3[1:0] = 01: push-pull
SS3[1:0] = 10: input-only (high-impedance)
SS3[1:0] = 11: open-drain SS3.0 SS2.1 SS2[1:0] = 00: quasi-bidirectional
SS2[1:0] = 01: push-pull
SS2[1:0] = 10: input-only (high-impedance)
SS2[1:0] = 11: open-drain SS2.0 SS1.1 SS1[1:0] = 00: quasi-bidirectional
SS1[1:0] = 01: push-pull
SS1[1:0] = 10: input-only (high-impedance)
SS1[1:0] = 11: open-drain SS1.0 SS0.1 SS0[1:0] = 00: quasi-bidirectional
SS0[1:0] = 01: push-pull
SS0[1:0] = 10: input-only (high-impedance)
SS0[1:0] = 11: open-drain SS0.0
NXP Semiconductors SC18IS602B2 C-bus to SPI bridgepulled LOW by an external device, the weak pull-up turns off, and only the very weak
pull-up remains on. In order to pull the pin LOW under these conditions, the external
device has to sink enough current to overpower the weak pull-up and pull the pin below its
input threshold voltage.
The third pull-up is referred to as the ‘strong’ pull-up. This pull-up is used to speed up
LOW-to-HIGH transitions on a quasi-bidirectional pin when the port latch changes from a
logic 0 to a logic 1. When this occurs, the strong pull-up turns on for two CPU clocks
quickly pulling the pin HIGH.
The quasi-bidirectional pin configuration is shown in Figure 15.
Although the SC18IS602B is a 3 V device, most of the pins are 5 V tolerant. If 5 V is
applied to a pin configured in quasi-bidirectional mode, there will be a current flowing from
the pin to VDD causing extra power consumption. Therefore, applying 5 V to pins
configured in quasi-bidirectional mode is discouraged.
A quasi-bidirectional pin has a Schmitt-triggered input that also has a glitch suppression
circuit.
7.1.11.2 Open-drain output configurationThe open-drain output configuration turns off all pull-ups and only drives the pull-down
transistor of the pin when the port latch contains a logic 0. To be used as a logic output, a
pin configured in this manner must have an external pull-up, typically a resistor tied to
VDD. The pull-down for this mode is the same as for the quasi-bidirectional mode.
The open-drain pin configuration is shown in Figure 16.
An open-drain pin has a Schmitt-triggered input that also has a glitch suppression circuit.
NXP Semiconductors SC18IS602B2 C-bus to SPI bridge
7.1.11.3 Input-only configurationThe input-only pin configuration is shown in Figure 17. It is a Schmitt-triggered input that
also has a glitch suppression circuit.
7.1.11.4 Push-pull output configurationThe push-pull output configuration has the same pull-down structure as both the
open-drain and the quasi-bidirectional output modes but provides a continuous strong
pull-up when the port latch contains a logic 1. The push-pull mode may be used when
more source current is needed from a pin output.
The push-pull pin configuration is shown in Figure 18.
A push-pull pin has a Schmitt-triggered input that also has a glitch suppression circuit.
NXP Semiconductors SC18IS602B2 C-bus to SPI bridge
7.2 SPI interfaceThe SPI interface can support Mode 0 through Mode 3 of the SPI specification and can
operate up to 1.8 Mbit/s. The SPI interface uses at least four pins: SPICLK, MOSI, MISO,
and Slave Select (SSn).
SSn are the slave select pins. In a typical configuration, an SPI master selects one SPI
device as the current slave.
There are actually four SSn pins (SS0, SS1, SS2 and SS3) to allow the SC18IS602B to
communicate with multiple SPI devices.
The SC18IS602B generates the SPICLK (SPI clock) signal in order to send and receive
data. The SCLK, MOSI, and MISO are typically tied together between two or more SPI
devices. Data flows from the SC18IS602B (master) to slave on the MOSI pin (Pin 6) and
the data flows from slave to SC18IS602B (master) on the MISO pin (Pin 5).
8. I2 C-bus to SPI communications exampleThe following example describes a typical sequence of events required to read the
contents of an SPI-based EEPROM. This example assumes that the SC18IS602B is
configured to respond to address 50h. A START condition is shown as ‘ST’, while a STOP
condition is ‘SP’. The data is presented in hexadecimal format. The first message is used to configure the SPI port for mode and frequency.
ST,50,F0,02,SP SPI frequency 115 kHz using Mode 0 An SPI EEPROM first requires that a Write Enable command be sent before data can
be written.
ST,50,04,06,SP EEPROM write enable using SS2, assuming the Write Enable is
06h Clear the interrupt. This is not required if using a polling method rather than interrupts.
ST,50,F1,SP Clear interrupt Write the 8 data bytes. The first byte (Function ID) tells the SC18IS602B which Slave
Select output to use. This example uses SS2 (shown as 04h). The first byte sent to
the EEPROM is normally 02h for the EEPROM write command. The next one or two
bytes represent the subaddress in the EEPROM. In this example, a two-byte
subaddress is used. Bytes 00 and 30 would cause the EEPROM to write to
subaddress 0030h. The next eight bytes are the eight data bytes that will be written to
subaddresses 0030h through 0037h.
ST,50,04,02,00,30,01,02,03,04,05,06,07,08,SP Write 8 bytes using SS2 When an interrupt occurs, do a Clear Interrupt or wait until the SC18IS602B responds
to its I2 C-bus address.
ST,50,F1,SP Clear interrupt
