SC18IM700IPW Fast Delivery |IC PHOENIX CO.,LIMITED

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SC18IM700IPW
Master I虏C-bus controller with UART interface
General descriptionThe SC18IM700is designedto serveasan interface between the standard UART portof microcontrolleror microprocessor and the serialI2 C-bus; this allows the microcontroller
or microprocessor to communicate directly with other I2 C-bus devices. The SC18IM700
can operate as an I2 C-bus master. The SC18IM700 controls all the I2 C-bus speciﬁc
sequences, protocol, arbitration and timing. The host communicates with SC18IM700 with
ASCII messages protocol; this makes the control sequences from the host to the
SC18IM700 become very simple. Features UART host interfaceI2 C-bus controller Eight programmable I/O pins High-speed UART: baud rate up to 460.8 kbit/s High-speed I2 C-bus: 400 kbit/s 16-byte TX FIFO 16-byte RX FIFO Programmable baud rate generator 2.3 V and 3.6 V operation Sleep mode (power-down) UART message format resembles I2 C-bus transaction formatI2 C-bus master functions Multi-master capability5 V tolerance on the input pins8N 1 UART format (8 data bits, no parity bit, 1 stop bit) Available in very small TSSOP16 package Applications Enable I2 C-bus master support in a systemI2 C-bus instrumentation and control Industrial control Medical equipment Cellular telephones Handheld computers
SC18IM700
Master I2 C-bus controller with UART interface
Rev. 02 — 10 August 2007 Product data sheet
NXP Semiconductors SC18IM700
Master I2 C-bus controller with UART interface Ordering information Block diagram
Table 1. Ordering information
SC18IM700IPW TSSOP16 plastic thin shrink small outline package;16 leads;
body width 4.4 mm
SOT403-1
NXP Semiconductors SC18IM700
Master I2 C-bus controller with UART interface Pinning information
6.1 Pinning
6.2 Pin description
Table 2. Pin description
GPIO0 1 I/O programmable I/O pin
GPIO1 2 I/O programmable I/O pin
RESET 3 I hardware reset input
VSS 4 - ground
GPIO2 5 I/O programmable I/O pin
GPIO3 6 I/O programmable I/O pin
SDA 7 I/O I2 C-bus data pin
SCL 8 O I2 C-bus clock output 9 I RS-232 receive input 10 O RS-232 transmit input
GPIO6 11 I/O programmable I/O pin
VDD 12 - power supply
WAKEUP 13 I Wake up SC18IM700 from Power-down mode. Pulling LOW by the
host to wake up the device. A 1 kΩ resistor must be connected
between VDD and this pin.
GPIO5 14 I/O programmable I/O pin
GPIO4 15 O programmable I/O pin
GPIO7 16 O programmable I/O pin
NXP Semiconductors SC18IM700
Master I2 C-bus controller with UART interface Functional description
The SC18IM700 is a bridge between a UART port and I2 C-bus. The UART interface
consists of a full-functional advanced UART. The UART communicates with the host
through the TX and RX pins. The serial data format is ﬁxed: one start bit, 8 data bits, and
one stop bit. After reset the baud rate defaultsto 9600 bit/s, and canbe changed through
the Baud Rate Generator (BRG) registers.
Aftera power-up sequenceora hardware reset, the SC18IM700 will send two continuous
bytes to the host to indicate a start-up condition. These two bytes are 0x4F and 0x4B;
‘OK’ in ASCII.
7.1 UART message format
The host initiates an I2 C-bus data transfer, reads from and writes to SC18IM700 internal
registers through a series of ASCII commands. Table 3 lists the ASCII commands
supported by SC18IM700, and also their hexadecimal value representation.
Unrecognized commands are ignored by the device.
To prevent the host from handing the SC18IM700 due to an unﬁnished command
sequence, the SC18IM700 has a time-out feature. The delay between any two bytes of
data coming from the host should be less than 655 ms. If this condition is not met, the
SC18IM700 will time-out and clear the receive buffer. The SC18IM700 then starts to wait
for the next command from the host.
7.1.1 Write N bytes to slave device
The host issues the write command by sending an S character followed by an I2 C-bus
slave device address, the total numberof bytestobe sent, andI2 C-bus data which begins
with the ﬁrst byte (DATA 0) and ends with the last byte (DAT A N). The frame is then
terminated with a P character. Once the host issues this command, the SC18IM700 will
access the I2 C-bus slave device and start sending the I2 C-bus data bytes.
Note that the second byte sent is the I2 C-bus device slave address. The least signiﬁcant
bit (W) of this byte must be set to 0 to indicate this is an I2 C-bus write command.
Table 3. ASCII commands supported by SC18IM700 0x53 I2 C-bus START 0x50 I2 C-bus STOP 0x52 read SC18IM700 internal register 0x57 write to SC18IM700 internal register 0x49 read GPIO port 0x4F write to GPIO port 0x5A power down
NXP Semiconductors SC18IM700
Master I2 C-bus controller with UART interface
7.1.2 Read N byte from slave device
The host issues the read command by sending an S character followed by an I2 C-bus
slave device address, and the total number of bytes to be read from the addressed2 C-bus slave. The frame is then terminated with a P character. Once the host issues this
command, the SC18IM700 will access theI2 C-bus slave device, get the correct numberof
bytes from the addressed I2 C-bus slave, and then return the data to the host.
Note that the second byte sent is the I2 C-bus device slave address. The least signiﬁcant
bit (R) of this byte must be set to 1 to indicate this is an I2 C-bus write command.
7.1.3 Write to 18IM internal register
The host issues the internal register write commandby sendingaW character followedby
the register and data pair. Each register to be written must be followed by the data byte.
The frame is then terminated with a P character.
Remark: Write and read from the internal 18IM registeris processed immediatelyas soon
as the intended register is determined by 18IM.
NXP Semiconductors SC18IM700
Master I2 C-bus controller with UART interface
7.1.4 Read from 18IM internal register
The host issues the internal register read command by sending an R character followed
by the registers to be read. The frame is then terminated with a P character.
Once the commandis issued, SC18IM700 will accessits internal registers and returns the
contents of these registers to the host.
7.1.5 Write to GPIO port
The host issues the output port write commandby sendinganO character followedby the
data to be written to the output port. This command enables the host to quickly set any
GPIO pins programmed as output without having to write to the SC18IM700 internal
IOState register.
7.1.6 Read from GPIO port
The host issues the input port read command by sending an I character. This command
enables the host to quickly read any GPIO pins programmed as input without having to
read the SC18IM700 internal IOState register.
Once the command is issued, SC18IM700 will read its internal IOState register and
returns its content to the host.
7.1.7 Repeated START: read after write
The SC18IM700 also supports ‘read after write’ command as speciﬁed in the NXP
Semiconductors I2 C-bus speciﬁcation. This allows a read command to be sent after a
write command without having to issue a STOP condition between the two commands.
The host issues a write command as normal, then immediately issues a read command
without sending a STOP (P) character after the write command.
NXP Semiconductors SC18IM700
Master I2 C-bus controller with UART interface
7.1.8 Repeated START: write after write
The SC18IM700 also supports ‘write after write’ command as speciﬁed in the NXP
Semiconductors I2 C-bus speciﬁcation. This allows a write command to be sent after a
write command without having to issue a STOP condition between the two commands.
The host issues a write command as normal, then immediately issues a second write
command without sending a STOP (P) character after the ﬁrst write command.
7.1.9 Power-down mode
The SC18IM700 canbe placedina low-power mode.In this mode the internal oscillatoris
stopped and SC18IM700 will no longer respond to the host messages. Enter the
Power-down mode by sending the power-down character Z (0x5A) followed by the two
deﬁned bytes, which are 0x5A and followedby 0xA5.If the exact messageis not received,
the device will not enter the power-down state.
Upon entering the power-down state, SC18IM700 places the WAKEUP pin in a HIGH
state.To have the device leave the power-down state, the WAKEUP pin shouldbe brought
LOW. A 1 kΩ resistor must be connected between the WAKEUP pin and VDD.
NXP Semiconductors SC18IM700
Master I2 C-bus controller with UART interface I2 C-bus serial interface
The I2 C-bus uses two wires (SDA and SCL) to transfer information between devices
connected to the bus, and it has the following features: Bidirectional data transfer between masters and slaves Multi-master bus (no central master) Arbitration between simultaneously transmitting masters without corruption of serial
data on the bus Serial clock synchronization allows devices with differentbit ratesto communicate via
one serial bus Serial clock synchronization canbe usedasa handshake mechanismto suspend and
resume serial transfer.
A typical I2 C-bus conﬁguration is shown in Figure 12. The SC18IM700 device provides a
byte-oriented I2 C-bus interface that supports data transfers up to 400 kHz.
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NXP Semiconductors SC18IM700
Master I2 C-bus controller with UART interface Internal registers available
Register summar
le 4.
Internal register
s summar
NXP Semiconductors SC18IM700
Master I2 C-bus controller with UART interface
9.2 Register descriptions
9.2.1 Baud Rate Generator (BRG)
The baud rate generatorisan 8-bit counter that generates the data ratefor the transmitter
and the receiver. The rateis programmed through the BRG register and the baud rate can
be calculated as follows:
Remark:T o calculate the baud rate the values in the BRG registers must ﬁrst be
converted from hex to decimal.
Remark: For the new baud rate to take effect, both BRG0 and BRG1 must be written in
sequence (BRG0, BRG1) with new values. The new baud rate willbein effect once BRG1
is written.
9.2.2 Programmable port conﬁguration (PortConf1 and PortConf2)
GPIO port 0 to port 7 may be conﬁgured by software to one of four types. These are:
quasi-bidirectional, push-pull, open-drain, and input-only. T wo bits are used to select the
desired conﬁguration for each port pin. PortConf1 is used to select the conﬁguration for
GPIO3to GPIO0, and PortConf2 is used to select the conﬁguration for GPIO7to GPIO4.
A port pin has Schmitt triggered input that also has a glitch suppression circuit.
9.2.2.1 Quasi-bidirectional output conﬁguration
Quasi-bidirectional output type canbe usedas bothan input and output without the need
to reconﬁgure the port. This is possible because when the port outputs a logic HIGH, it is
weakly driven, allowing an external device to pull the pin LOW. When the pin is driven
LOW, it is driven strongly and able to sink a fairly large current. These features are
somewhat similartoan open-drain output except that there are three pull-up transistorsin
the quasi-bidirectional output that serve different purposes.
The SC18IM700isa3V device, but the pins are5V tolerant.In quasi-bidirectional mode,a user applies5Von the pin, there willbea current ﬂowing from the pinto VDD, causing
extra power consumption. Therefore, applying 5 V in quasi-bidirectional mode is
discouraged.
A quasi-bidirectional port pin has a Schmitt triggered input that also has a glitch
suppression circuit.
Baud rate 7.3728 106× BRG1 BRG0, ()+ -----------------------------------------------------=
Table 5. Port conﬁgurations 0 quasi-bidirectional output conﬁguration 1 input-only conﬁguration 0 push-pull output conﬁguration 1 open-drain output conﬁguration
NXP Semiconductors SC18IM700
Master I2 C-bus controller with UART interface
9.2.2.2 Input-only conﬁguration
The input-only port conﬁguration has no output drivers. It is a Schmitt triggered input that
also has a glitch suppression circuit.
9.2.2.3 Push-pull output conﬁguration
The push-pull output conﬁguration has the same pull-down structure as both the
open-drain and the quasi-bidirectional output modes, but provides a continuous strong
pull-up when the port latch contains a logic 1. The push-pull mode may be used when
more source current is needed from a port output. A push-pull port pin has a Schmitt
triggered input that also has a glitch suppression circuit.

Partno	Mfg	Dc	Qty	Available	Descript
SC18IM700IPW	NXP	N/a	2500	avai	Master I虏C-bus controller with UART interface