SC16C754BIB80 ,5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOsBlock diagramSC16C754BTRANSMIT TRANSMITFIFO SHIFT TXA to TXDREGISTERS REGISTERD0 to D7 DATA BUSIOR ..
SC16C754BIB80 ,5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs
SC16C754BIBM ,5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOsLimiting values”.SC16C754BNXP Semiconductors5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64 ..
SC16C754IA68 ,Quad UART with 64-byte FIFO
SC16C754IA68 ,Quad UART with 64-byte FIFO
SC16C850IBS ,2.5 V to 3.3 V UART, 5 Mbit/s (max.) with 128-byte FIFOs, infrared (IrDA), and 16 mode or 68 mode parallel bus interfacefeatures may be tailored by software to meet specific user requirements. An internal loopback capab ..
SDB20S30 ,Silicon Carbide Schottky DiodeSDP20S30Preliminary dataSDB20S30Silicon Carbide Schottky Diode
SC16C754BIA68-SC16C754BIB80-SC16C754BIBM
5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs
General descriptionThe SC16C754B is a quad Universal Asynchronous Receiver/Transmitter (UART) with
64-byte FIFOs, automatic hardware/software flow control, and data rates up to 5 Mbit/s
(3.3V and5 V). The SC16C754B offers enhanced features.It hasa Transmission Control
Register (TCR) that stores receiver FIFO threshold levelsto start/stop transmission during
hardware and software flow control. With the FIFO Ready (FIFO Rdy) register, the
software gets the statusof TXRDY/RXRDYforall four portsin one access. On-chip status
registers provide the user with error indications, operational status, and modem interface
control. System interrupts may be tailored to meet user requirements. An internal
loopback capability allows on-board diagnostics.
The UART transmits data, sent to it over the peripheral 8-bit bus, on the TX signal and
receives characters on the RX signal. Characters can be programmed to be 5, 6, 7, or bits. The UART hasa 64-byte receive FIFO and transmit FIFO and canbe programmed
to interrupt at different trigger levels. The UART generates its own desired baud rate
based upon a programmable divisor and its input clock. It can transmit even, odd, or no
parity and 1, 1.5, or 2 stop bits. The receiver can detect break, idle, or framing errors,
FIFO overflow, and parity errors. The transmitter can detect FIFO underflow. The UART
also contains a software interface for modem control operations, and has software flow
control and hardware flow control capabilities.
The SC16C754B is available in plastic LQFP64, LQFP80 and PLCC68 packages.
Features 4 channel UART5V , 3.3 V and 2.5 V operation Pin compatible with SC16C654IA68, TL16C754, and SC16C554IA68 with additional
enhancements, and software compatible with TL16C754 Up to 5 Mbit/s data rate (at 3.3 V and 5 V; at 2.5 V maximum data rate is 3 Mbit/s)5 V tolerant on input only pins1 64-byte transmit FIFO 64-byte receive FIFO with error flags Industrial temperature range (−40 °C to +85 °C) Programmable and selectable transmit and receive FIFO trigger levels for DMA and
interrupt generation
SC16C754B
5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte
FIFOs
Rev. 04 — 6 October 2008 Product data sheet For data bus pins D7 to D0, see Table 24 “Limiting values”.
NXP Semiconductors SC16C754B
5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs Software (Xon/Xoff)/hardware (RTS/CTS) flow control Programmable Xon/Xoff characters Programmable auto-RTS and auto-CTS Optional data flow resume by Xon any character DMA signalling capability for both received and transmitted data Supports 5 V, 3.3 V and 2.5 V operation Software selectable baud rate generator Prescaler provides additional divide-by-4 function Fast data bus access time Programmable Sleep mode Programmable serial interface characteristics 5, 6, 7, or 8-bit characters Even, odd, or no-parity bit generation and detection 1, 1.5, or 2 stop bit generation False start bit detection Complete status reporting capabilities in both normal and Sleep mode Line break generation and detection Internal test and loopback capabilities Fully prioritized interrupt system controls Modem control functions (CTS, RTS, DSR, DTR, RI, and CD) Sleep mode
Ordering information
Table 1. Ordering informationSC16C754BIBM LQFP64 plastic low profile quad flat package; 64 leads; body 7×7× 1.4 mm SOT414-1
SC16C754BIB80 LQFP80 plastic low profile quad flat package; 80 leads; body 12×12× 1.4 mm SOT315-1
SC16C754BIA68 PLCC68 plastic leaded chip carrier; 68 leads SOT188-2
NXP Semiconductors SC16C754B
5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs Block diagram
NXP Semiconductors SC16C754B
5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs Pinning information
5.1 Pinning
NXP Semiconductors SC16C754B
5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs
NXP Semiconductors SC16C754B
5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs
5.2 Pin description
Table 2. Pin description 24 30 34 I
Address 0 select bit. Internal registers address selection. 23 29 33 I
Address 1 select bit. Internal registers address selection. 22 28 32 I
Address 2 select bit. Internal registers address selection.CDA64 79 9 I
Carrier Detect (active LOW). These inputs are associated with
individual UART channels A through D. A logic LOW on these pins
indicates thata carrier has been detectedbythe modemfor that channel.
The state of these inputs is reflected in the Modem Status Register
(MSR).
CDB 18 23 27
CDC 31 39 43
CDD 49 63 61
CLKSEL- 26 30 I
Clock Select. CLKSEL selects the divide-by-1or divide-by-4 prescalable
clock. During the reset, a logic 1 (VCC) on CLKSEL selects the
divide-by-1 prescaler.A logic0 (GND)on CLKSEL selects the divide-by-4
prescaler. The value of CLKSEL is latched into MCR[7] at the trailing
edge of RESET. A logic 1 (VCC) on CLKSEL will latch a logic 0 into
MCR[7]. A logic 0 (GND) on CLKSEL will latch a logic 1 into MCR[7].
MCR[7] can be changed after RESET to alter the prescaler value. This
pin is associated with LQFP80 and PLCC68 packages only. This pin is
connected to VCC internally on LQFP64 package.
NXP Semiconductors SC16C754B
5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOsCSA 7 9 16 I
Chip Select (active LOW). These pins enable data transfers between
the user CPU and the SC16C754B for the channel(s) addressed.
Individual UART sections (A, B, C, D) are addressed by providing a logic
LOW on the respective CSA through CSD pins.
CSB 11 13 20
CSC 38 49 50
CSD 42 53 54
CTSA 2 4 11 I
Clearto Send (active LOW). These inputs are associated with individual
UART channels A through D. A logic 0 (LOW) on the CTS pins indicates
the modem or data set is ready to accept transmit data from the
SC16C754B. Status can be tested by reading MSR[4]. These pins only
affect the transmit and receive operations when auto-CTS function is
enabled via the Enhanced Feature Register EFR[7] for hardware flow
control operation.
CTSB 16 18 25
CTSC 33 44 45
CTSD 47 58 59toD7 53, 54,
55, 56,
57, 58,
59, 60
68, 69,
70, 71,
72, 73,
74, 75
66, 67,
68,1,2,
3, 4, 5
I/O
Data bus (bidirectional). These pins are the 8-bit, 3-state data bus fortransferring information to or from the controlling CPU. D0 is the least
significant bit and the first data bit in a transmit or receive serial data
stream.
DSRA 1 3 10 I
Data Set Ready (active LOW). These inputs are associated withindividual UART channels A through D. A logic 0 (LOW) on these pins
indicates the modem or data set is powered-on and is ready for data
exchange with the UART. The state of these inputs is reflected in the
Modem Status Register (MSR).
DSRB 17 19 26
DSRC 32 43 44
DSRD 48 59 60
DTRA 3 5 12 O
Data Terminal Ready (active LOW). These outputs are associated withindividual UART channels A through D. A logic 0 (LOW) on these pins
indicates that the SC16C754B is powered-on and ready. These pins can controlledvia the Modem Control Register (MCR). Writinga logic1to
MCR[0] will set the DTR output to logic 0 (LOW), enabling the modem.
The outputof these pins willbea logic1 after writinga logic0to MCR[0],
or after a reset.
DTRB 15 17 24
DTRC 34 45 46
DTRD 46 57 58
GND 14, 28,
45, 61
16, 36,
56, 76
6, 23,
40, 57
Signal and power ground.INTA 6 8 15 O
Interrupt A, B, C, and D (active HIGH). These pins provide individualchannel interrupts INTA through INTD. INT A through INTD are enabled
when MCR[3] is set to a logic 1, interrupt sources are enabled in the
Interrupt Enable Register (IER). Interrupt conditions include: receiver
errors, available receiver buffer data, available transmit buffer space, or
when a modem status flag is detected. INTAto INTD are in the
high-impedance state after reset.
INTB 12 14 21
INTC 37 48 49
INTD 43 54 55
INTSEL - 67 65 I
Interrupt Select (active HIGH with internal pull-down). INTSEL canbe
used in conjunction with MCR[3] to enable or disable the 3-state
interrupts INTAto INTD or override MCR[3] and force continuous
interrupts. Interrupt outputs are enabled continuouslyby making thispina
logic 1. Driving this pin LOW allows MCR[3] to control the 3-state
interrupt output. In this mode, MCR[3] is set to a logic 1 to enable the
3-state outputs. This pin is associated with LQFP80 and PLCC68
packages only. This pin is connected to GND internally on the LQFP64
package.
IOR 40 51 52 I
Input/Output Read strobe (active LOW). A HIGH-to-LOW transition onIOR will load the contents of an internal register defined by address bits
A[2:0] onto the SC16C754B data bus (D[7:0]) for access by external
CPU.
Table 2. Pin description …continued
NXP Semiconductors SC16C754B
5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOsIOW 9 11 18 I
Input/Output Write strobe (active LOW). A LOW-to-HIGH transition onIOW will transfer the contents of the data bus (D[7:0]) from the external
CPUtoan internal register thatis definedby address bits A[2:0] and CSA
and CSD.
n.c. - 1,2, 20,
21, 22,
27, 40,
41, 42,
60, 61,
62, 80 - not connected
RESET 27 33 37 I
Reset. This pin will reset the internal registers and all the outputs. TheUART transmitter output and the receiver input will be disabled during
reset time. RESET is an active HIGH input.
RIA 63 78 8 I
Ring Indicator (active LOW). These inputs are associated withindividual UART channels,A throughD.A logic0on these pins indicates
the modem has received a ringing signal from the telephone line. A
LOW-to-HIGH transition on these input pins generates a modem status
interrupt, if enabled. The state of these inputs is reflected in the Modem
Status Register (MSR).
RIB 19 24 28
RIC 30 38 42
RID 50 64 62
RTSA 5 7 14 O
Request to Send (active LOW). These outputs are associated withindividual UART channels, A through D. A logic 0 on the RTS pin
indicates the transmitter has data ready and waiting to send. Writing a
logic1inthe Modem Control Register MCR[1] willset thispintoa logic0,
indicating data is available. After a reset these pins are set to a logic 1.
These pins only affect the transmit and receive operations when
auto-RTS function is enabled via the Enhanced Feature Register
(EFR[6]) for hardware flow control operation.
RTSB 13 15 22
RTSC 36 47 48
RTSD 44 55 56
RXA 62 77 7 I
Receive data input. These inputs are associated with individual serialchannel data to the SC16C754B. During the local loopback mode, these
RX input pins are disabled and TX data is connected to the UART RX
input internally.
RXB 20 25 29
RXC 29 37 41
RXD 51 65 63
RXRDY - 34 38 O
Receive Ready (active LOW). RXRDY contains the wire-ORed statusof
all four receive channel FIFOs, RXRDYAto RXRDY D. It goes LOW
when the trigger level has been reached or a time-out interrupt occurs. It
goes HIGH when all RX FIFOs are empty and there is an error in RX
FIFO. This pin is associated with LQFP80 and PLCC68 packages only.
TXA 8 1017O
Transmit data. These outputs are associated with individual serialtransmit channel data from the SC16C754B. During the local loopback
mode, the TX output pin is disabled and TX data is internally connected
to the UART RX input.
TXB 10 12 19
TXC 39 50 51
TXD 41 52 53
TXRDY - 35 39 O
Transmit Ready (active LOW). TXRDY contains the wire-ORed statusof
all four transmit channel FIFOs, TXRDYAto TXRDY D. It goes LOW
when there are a trigger level number of spaces available. It goes HIGH
when all four TX buffers are full. This pin is associated with LQFP80 and
PLCC68 packages only.
Table 2. Pin description …continued
NXP Semiconductors SC16C754B
5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs Functional descriptionThe SC16C754B UART is pin-compatible with the SC16C554 and SC16C654 UARTs. It
provides more enhanced features. All additional features are provided through a special
enhanced feature register.
The UART will perform serial-to-parallel conversion on data characters received from
peripheral devices or modems, and parallel-to-parallel conversion on data characters
transmitted by the processor. The complete status of each channel of the SC16C754B
UART can be read at any time during functional operation by the processor.
The SC16C754B canbe placedinan alternate mode (FIFO mode) relieving the processor
of excessive software overhead by buffering received/transmitted characters. Both the
receiver and transmitter FIFOs can store up to 64 bytes (including three additional bits of
error status per byte for the receiver FIFO) and have selectable or programmable trigger
levels. Primary outputs RXRDY and TXRDY allow signalling of DMA transfers.
The SC16C754B has selectable hardware flow control and software flow control.
Hardware flow control significantly reduces software overhead and increases system
efficiencyby automatically controlling serial data flow using the RTS output and CTS input
signals. Software flow control automatically controls data flow by using programmable
Xon/Xoff characters.
The UART includes a programmable baud rate generator that can divide the timing
reference clock input by a divisor between 1 and (216− 1).
6.1 Trigger levelsThe SC16C754B provides independent selectable and programmable trigger levels for
both receiver and transmitter DMA and interrupt generation. After reset, both transmitter
and receiver FIFOs are disabled and so, in effect, the trigger level is the default value of
one byte. The selectable trigger levels are available via the FIFO Control Register (FCR).
The programmable trigger levels are available via the Trigger Level Register (TLR).
VCC 4, 21,
35, 52 46,66 13, 47,
Power supply input.XTAL1 25 31 35 I
Crystal or external clock input. Functions as a crystal input or as anexternal clock input. A crystal can be connected between XTAL1 and
XTAL2 to form an internal oscillator circuit (see Figure 14). Alternatively,
an external clock can be connected to this pin to provide custom data
rates.
XTAL2 26 32 36 O
Output of the crystal oscillator or buffered clock (see also XTAL1).XTAL2 is used as a crystal oscillator output or a buffered clock output.
Table 2. Pin description …continued
NXP Semiconductors SC16C754B
5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs
6.2 Hardware flow controlHardware flow control is comprised of auto-CTS and auto-RTS. Auto-CTS and auto-RTS
can be enabled/disabled independently by programming EFR[7:6].
With auto-CTS, CTS must be active before the UART can transmit data.
Auto-RTS only activates the RTS output when thereis enough roomin the FIFOto receive
data and de-activates the RTS output when the RX FIFO is sufficiently full. The halt and
resume trigger levels in the TCR determine the levels at which RTS is
activated/deactivated.
If both auto-CTS and auto-RTS are enabled, when RTS is connected to CTS, data
transmission does not occur unless the receiver FIFO has empty space. Thus, overrun
errors are eliminated during hardware flow control. If not enabled, overrun errors occur if
the transmit data rate exceeds the receive FIFO servicing latency.
NXP Semiconductors SC16C754B
5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs
6.2.1 Auto-RTSAuto-RTS data flow control originatesin the receiver block (see Figure1 “Block diagramof
SC16C754B”). Figure 6 shows RTS functional timing. The receiver FIFO trigger levels
used in auto-RTS are stored in the TCR. RTS is active if the RX FIFO level is below the
halt trigger levelin TCR[3:0]. When the receiver FIFO halt trigger levelis reached, RTSis
de-asserted. The sending device (for example, another UART) may send an additional
byte after the trigger level is reached (assuming the sending UART has another byte to
send) becauseit may not recognize the de-assertionof RTS untilit has begun sending the
additional byte. RTS is automatically reasserted once the receiver FIFO reaches the
resume trigger level programmed via TCR[7:4]. This re-assertion allows the sending
device to resume transmission.
6.2.2 Auto-CTSThe transmitter circuitry checks CTS before sending the next data byte. When CTS is
active, the transmitter sends the next byte. To stop the transmitter from sending the
following byte, CTS must be de-asserted before the middle of the last stop bit that is
currently being sent. The auto-CTS function reduces interrupts to the host system. When
flow control is enabled, CTS level changes do not trigger host interrupts because the
device automatically controlsits own transmitter. Without auto-CTS, the transmitter sends
any data present in the transmit FIFO and a receiver overrun error may result.
NXP Semiconductors SC16C754B
5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs
6.3 Software flow controlSoftware flow control is enabled through the enhanced feature register and the modem
control register. Different combinations of software flow control can be enabled by setting
different combinations of EFR[3:0]. Table 3 shows software flow control options.
Remark: When using software flow control, the Xon/Xoff characters cannot be used for
data characters.
There are two other enhanced features relating to software flow control:
‘Xon Any’ function (MCR[5]): Operation will resume after receiving any characterafter recognizing the Xoff character. It is possible that an Xon1 character is
recognized as an ‘Xon Any’ character, which could cause an Xon2 character to be
written to the RX FIFO.
Special character (EFR[5]): Incoming data is compared to Xoff2. Detection of thespecial character sets the Xoff interrupt (IIR[4]) but does not halt transmission. The
Xoff interruptis clearedbya readof the IIR. The special characteris transferredto the
RX FIFO.
6.3.1 RXWhen software flow control operation is enabled, the SC16C754B will compare incoming
data with Xoff1/Xoff2 programmed characters (in certain cases, Xoff1 and Xoff2 must be
received sequentially). When the correct Xoff characteris received, transmissionis halted
after completing transmission of the current character. Xoff detection also sets IIR[4] (if
enabled via IER[5]) and causes INT to go HIGH.
To resume transmission, an Xon1/Xon2 character must be received (in certain cases
Xon1 and Xon2 must be received sequentially). When the correct Xon characters are
received, IIR[4] is cleared, and the Xoff interrupt disappears.
Table 3. Software flow control options (EFR[3:0]) 0 X X no transmit flow control 0 X X transmit Xon1, Xoff1 1 X X transmit Xon2, Xoff2 1 X X transmit Xon1, Xon2, Xoff1, Xoff2 X 0 0 no receive flow control X 1 0 receiver compares Xon1, Xoff1 X 0 1 receiver compares Xon2, Xoff2 0 1 1 transmit Xon1, Xoff1
receiver compares Xon1 or Xon2, Xoff1 or Xoff2 1 1 1 transmit Xon2, Xoff2
receiver compares Xon1 or Xon2, Xoff1 or Xoff2 1 1 1 transmit Xon1, Xon2, Xoff1, Xoff2
receiver compares Xon1 and Xon2, Xoff1 and Xoff2 0 1 1 no transmit flow control
receiver compares Xon1 and Xon2, Xoff1 and Xoff2
NXP Semiconductors SC16C754B
5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs
6.3.2 TXXoff1/Xoff2 character is transmitted when the RX FIFO has passed the
halt trigger levelprogrammed in TCR[3:0].
Xon1/Xon2 character is transmitted when the RX FIFO reaches the
resume trigger levelprogrammed in TCR[7:4].
The transmission of Xoff/Xon(s) follows the exact same protocol as transmission of an
ordinary byte from the FIFO. This means that evenif the word lengthis settobe5,6,or7
characters, then the 5, 6, or 7 least significant bits of Xoff1/Xoff2 and Xon1/Xon2 will be
transmitted. (Note that the transmissionof5,6,or7 bitsofa characteris seldom done, but
this functionality is included to maintain compatibility with earlier designs.)
It is assumed that software flow control and hardware flow control will never be enabled
simultaneously. Figure 8 shows an example of software flow control.
6.3.3 Software flow control example
6.3.3.1 AssumptionsUART1 is transmitting a large text file to UART2. Both UARTs are using software flow
control with single character Xoff (0Fh) and Xon (0Dh) tokens. Both have Xoff threshold
(TCR[3:0]= F) set to 60, and Xon threshold (TCR[7:4]= 8) set to 32. Both have the
interrupt receive threshold (TLR[7:4]= D) set to 52.
NXP Semiconductors SC16C754B
5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOsUART1 begins transmission and sends52 characters,at which point UART2 will generate
an interrupt to its processor to service the RX FIFO, but assumes the interrupt latency is
fairly long. UART1 will continue sending characters until a total of 60 characters have
been sent. At this time, UART2 will transmit a 0Fh to UART1, informing UART1 to halt
transmission. UART1 will likely send the 61st character while UART2 is sending the Xoff
character. Now UART2 is serviced and the processor reads enough data out of the RX
FIFO that the level drops to 32. UART2 will now send a 0Dh to UART1, informing UART1
to resume transmission.
6.4 ResetTable 4 summarizes the state of register after reset.
Remark: Registers DLL, DLM, SPR, Xon1, Xon2, Xoff1, Xoff2 are not reset by the
top-level reset signal RESET, that is, they hold their initialization values during reset.
Table 5 summarizes the state of registers after reset.
Table 4. Register reset functionsInterrupt enable register RESET all bits cleared
Interrupt identification register RESET bit 0 is set; all other bits cleared
FIFO control register RESET all bits cleared
Line control register RESET reset to 0001 1101 (1Dh)
Modem control register RESET all bits cleared
Line status register RESET bit 5 and bit 6 set; all other bits cleared
Modem status register RESET bits 3:0 cleared; bits 7:4 input signals
Enhanced feature register RESET all bits cleared
Receiver holding register RESET pointer logic cleared
Transmitter holding register RESET pointer logic cleared
Transmission control register RESET all bits cleared
Trigger level register RESET all bits cleared
Table 5. Signal RESET functions RESET HIGH
RTS RESET HIGH
DTR RESET HIGH
RXRDY RESET HIGH
TXRDY RESET LOW
NXP Semiconductors SC16C754B
5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs
6.5 InterruptsThe SC16C754B has interrupt generation and prioritization (six prioritized levels of
interrupts) capability. The Interrupt Enable Register (IER) enables eachof thesix typesof
interrupts and the INT signal in response to an interrupt generation. The IER can also
disable the interrupt system by clearing bits 7:5 and 3:0. When an interrupt is generated,
the IIR indicates that an interrupt is pending and provides the type of interrupt through
IIR[5:0].T able 6 summarizes the interrupt control functions.
It is important to note that for the framing error, parity error, and break conditions, LSR[7]
generates the interrupt. LSR[7] is set when there is an error anywhere in the RX FIFO,
andis cleared only when there areno more errors remainingin the FIFO. LSR[4:2] always
represent the error status for the received character at the top of the RX FIFO. Reading
the RX FIFO updates LSR[4:2]to the appropriate statusfor the new characterat the topof
the FIFO. If the RX FIFO is empty, then LSR[4:2] are all zeros.
For the Xoff interrupt,ifan Xoff flow character detection caused the interrupt, the interrupt
is cleared by an Xon flow character detection. If a special character detection caused the
interrupt, the interrupt is cleared by a read of the IIR.
Table 6. Interrupt control functions 0001 None none none none 0110 1 receiver line status OE, FE, PE, or BI errors occur in
characters in the RX FIFO
FE, PE, BI: all erroneous
characters are read from the FIFO.
OE: read LSR 1100 2 RX time-out stale data in RX FIFO read RHR 0100 2 RHR interrupt DRDY (data ready)
(FIFO disable)
RX FIFO above trigger level
(FIFO enable)
read RHR 0010 3 THR interrupt TFE (THR empty)
(FIFO disable) FIFO passes above trigger level
(FIFO enable)
read IIR
or a write to the THR 0000 4 modem status MSR[3:0]=0 read MSR 0000 5 Xoff interrupt receive Xoff character(s)/special
character
receive Xon character(s)/Read of
IIR 0000 6 CTS, RTS RTS pinor CTSpin change state from
active (LOW) to inactive (HIGH)
read IIR
NXP Semiconductors SC16C754B
5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs
6.5.1 Interrupt mode operation interrupt mode(if anybitof IER[3:0]is ‘1’) the processoris informedof the statusof the
receiver and transmitter by an interrupt signal, INT . Therefore, it is not necessary to
continuously poll the Line Status Register (LSR) to see if any interrupt needs to be
serviced. Figure 9 shows interrupt mode operation.
6.5.2 Polled mode operationIn polled mode (IER[3:0]= 0000) the status of the receiver and transmitter can be
checkedby polling the Line Status Register (LSR). This modeisan alternativeto the FIFO
interrupt mode of operation where the status of the receiver and transmitter is
automatically knownby meansof interrupts sentto the CPU. Figure10 shows FIFO polled
mode operation.
NXP Semiconductors SC16C754B
5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs
6.6 DMA operationThere are two modes of DMA operation, DMA mode 0 or DMA mode 1, selected by
FCR[3]. DMA mode0or FIFO disable (FCR[0]=0) DMA occursin single character transfers.In
DMA mode 1, multi-character (or block) DMA transfers are managed to relieve the
processor for longer periods of time.
6.6.1 Single DMA transfers (DMA mode 0/FIFO disable)Figure 11 shows TXRDY and RXRDY in DMA mode 0/FIFO disable.
6.6.1.1 TransmitterWhen empty, the TXRDY signal becomes active. TXRDY will go inactive after one
character has been loaded into it.
6.6.1.2 ReceiverRXRDY is active when there is at least one character in the FIFO. It becomes inactive
when the receiver is empty.
NXP Semiconductors SC16C754B
5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs
6.6.2 Block DMA transfers (DMA mode1)Figure 12 shows TXRDY and RXRDY in DMA mode1.
6.6.2.1 TransmitterTXRDY is active when there is a trigger level number of spaces available. It becomes
inactive when the FIFO is full.
6.6.2.2 ReceiverRXRDY becomes active when the trigger level has been reached, or when a time-out
interrupt occurs. It will go inactive when the FIFO is empty or an error in the RX FIFO is
flagged by LSR[7].
6.7 Sleep modeSleep modeisan enhanced featureof the SC16C754B UART.Itis enabled when EFR[4],
the enhanced functions bit, is set
and when IER[4] is set. Sleep mode is entered when: The serial data input line, RX, is idle (see Section 6.8 “Break and time-out
conditions”).
The TX FIFO and TX shift register are empty.
There are no interrupts pending except THR and time-out interrupts.
Remark: Sleep mode will
not be entered if there is data in the RX FIFO. Sleep mode, the UART clock and baud rate clock are stopped. Since most registers are
clocked using these clocks, the power consumption is greatly reduced. The UART will
wake up when any change is detected on the RX line, when there is any change in the
state of the modem input pins, or if data is written to the TX FIFO.
Remark: Writing to the divisor latches, DLL and DLM, to set the baud clock, must not be
done during Sleep mode. Therefore, it is advisable to disable Sleep mode using IER[4]
before writing to DLL or DLM.
NXP Semiconductors SC16C754B
5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs
6.8 Break and time-out conditionsAn RX idle condition is detected when the receiver line, RX, has been HIGH for character time. The receiver line is sampled midway through each bit.
When a break condition occurs, the TX line is pulled LOW. A break condition is activated
by setting LCR[6].
6.9 Programmable baud rate generatorThe SC16C754B UART contains a programmable baud generator that takes any clock
input and divides it by a divisor in the range between 1 and (216− 1). An additional
divide-by-4 prescaler is also available and can be selected by MCR[7], as shown in
Figure 13. The output frequency of the baud rate generator is 16 × the baud rate. The
formula for the divisor is given in Equation1:
(1)
Where:
prescaler= 1, when MCR[7] is set to 0 after reset (divide-by-1 clock selected)
prescaler= 4, when MCR[7] is set to 1 after reset (divide-by-4 clock selected).
Remark: The default value of prescaler after reset is divide-by-1.
Figure 13 shows the internal prescaler and baud rate generator circuitry.
DLL and DLM mustbe writtentoin orderto program the baud rate. DLL and DLM are the
least significant and most significant byte of the baud rate divisor. If DLL and DLM are
both zero, the UART is effectively disabled, as no baud clock will be generated.
Remark: The programmable baud rate generator is provided to select both the transmit
and receive clock rates.
Table 7 and Table 8 show the baud rate and divisor correlation for crystal with frequency
1.8432 MHz and 3.072 MHz, respectively.
Figure 14 shows the crystal clock circuit reference.
divisor
XTAL1 crystal input frequency
prescaler -------------------------------------------------------------------------------------
desired baud rate 16× () ------------------------------------------------------------------------------------------=
NXP Semiconductors SC16C754B
5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs
Table 7. Baud rates using a 1.8432 MHz crystal 2304 1536
110 1047 0.026
134.5 857 0.058
150 768
300 384
600 192
1200 96
1800 64
2000 58 0.69
2400 48
3600 32
4800 24
7200 16
9600 12
19200 6
38400 3
56000 2 2.86
Table 8. Baud rates using a 3.072 MHz crystal 3840 2560
110 1745 0.026
134.5 1428 0.034
150 1280
300 640
600 320
1200 160
1800 107 0.312
2000 96
2400 80
3600 53 0.628
4800 40
7200 27 1.23
9600 20
19200 10
38400 5
NXP Semiconductors SC16C754B
5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs Register descriptionsEach register is selected using address lines A0, A1, A2, and in some cases, bits from
other registers. The programming combinations for register selection are shown in
Table9.
[1] MCR[7] can only be modified when EFR[4] is set.
[2] Accessed by a combination of address pins and register bits.
[3] Accessible only when LCR[7]is logic1.
[4] Accessible only when LCR is set to 1011 1111 (BFh).
[5] Accessible only when EFR[4]= 1 and MCR[6]= 1, that is, EFR[4] and MCR[6] are read/write enables.
[6] Accessible only when CSAto CSD= 0, MCR[2]= 1, and loopback is disabled (MCR[4]=0).
Table 9. Register map - read/write properties 0 0 Receive Holding Register (RHR) Transmit Holding Register (THR) 0 1 Interrupt Enable Register (IER) Interrupt Enable Register (IER) 1 0 Interrupt Identification Register (IIR) FIFO Control Register (FCR) 1 1 Line Control Register (LCR) Line Control Register (LCR) 0 0 Modem Control Register (MCR)[1] Modem Control Register (MCR)[1] 0 1 Line Status Register (LSR) not applicable 1 0 Modem Status Register (MSR) not applicable 1 1 ScratchPad Register (SPR) ScratchPad Register (SPR) 0 0 Divisor Latch LSB (DLL) [2][3] Divisor Latch LSB (DLL) [2][3] 0 1 Divisor Latch MSB (DLM) [2][3] Divisor Latch MSB (DLM) [2][3] 1 0 Enhanced Feature Register (EFR) [2][4] Enhanced Feature Register (EFR) [2][4] 0 0 Xon1 word [2][4] Xon1 word [2][4] 0 1 Xon2 word [2][4] Xon2 word [2][4] 1 0 Xoff1 word [2][4] Xoff1 word [2][4] 1 1 Xoff2 word [2][4] Xoff2 word [2][4] 1 0 Transmission Control Register
(TCR) [2][5] Transmission Control Register
(TCR) [2][5] 1 1 Trigger Level Register (TLR) [2][5] Trigger Level Register (TLR) [2][5] 1 1 FIFO ready register [2][6]
NXP Semiconductors SC16C754B
5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOsTable 10 lists and describes the SC16C754B internal registers.
[1] These registers are accessible only when LCR[7]=0.
[2] This bit can only be modified if register bit EFR[4] is enabled, that is, if enhanced functions are enabled.
[3] The Special register set is accessible only when LCR[7] is set to a logic 1.
[4] Enhanced feature register; Xon1/Xon2 and Xoff1/Xoff2 are accessible only when LCR is set to BFh.
Table 10. SC16C754B internal registers
General register set[1]
Special register set[3]
Enhanced register set[4]
NXP Semiconductors SC16C754B
5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs
Remark: Refer to the notes under Table 9 for more register access information.
7.1 Receiver Holding Register (RHR)The receiver section consists of the Receiver Holding Register (RHR) and the Receiver
Shift Register (RSR). The RHR is actually a 64-byte FIFO. The RSR receives serial data
from the RX terminal. The data is converted to parallel data and moved to the RHR. The
receiver section is controlled by the Line Control Register (LCR). If the FIFO is disabled,
location zero of the FIFO is used to store the characters.
Remark: In this case, characters are overwritten if overflow occurs.
If overflow occurs, characters are lost. The RHR also stores the error status bits
associated with each character.
7.2 Transmit Holding Register (THR)The transmitter section consists of the Transmit Holding Register (THR) and the Transmit
Shift Register (TSR). The THR is actually a 64-byte FIFO. The THR receives data and
shifts it into the TSR, where it is converted to serial data and moved out on the TX
terminal. If the FIFO is disabled, the FIFO is still used to store the byte. Characters are
lost if overflow occurs.
NXP Semiconductors SC16C754B
5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs
7.3 FIFO Control Register (FCR)Thisisa write-only register thatis usedfor enabling the FIFOs, clearing the FIFOs, setting
transmitter and receiver trigger levels, and selecting the type of DMA signalling. Table11
shows FIFO control register bit settings.
Table 11. FIFO control register bits description7:6 FCR[7] (MSB),
FCR[6] (LSB)
RX trigger. Sets the trigger level for the RX FIFO.
00 — 8 characters
01 — 16 characters
10 — 56 characters
11 — 60 characters
5:4 FCR[5] (MSB),
FCR[4] (LSB)
TX trigger. Sets the trigger level for the TX FIFO.
00 — 8 spaces
01 — 16 spaces
10 — 32 spaces
11 — 56 spaces
FCR[5:4] can only be modified and enabled when EFR[4] is set. This is
because the transmit trigger level is regarded as an enhanced function. FCR[3] DMA mode select.
logic 0= set DMA mode0
logic 1= set DMA mode1 FCR[2] Reset TX FIFO.
logic 0= no FIFO transmit reset (normal default condition)
logic1= clears the contentsof the transmit FIFO and resets the FIFO
counter logic (the transmit shift register is not cleared or altered). This
bit will return to a logic 0 after clearing the FIFO. FCR[1] Reset RX FIFO.
logic 0= no FIFO receive reset (normal default condition)
logic 1= clears the contents of the receive FIFO and resets the FIFO
counter logic (the receive shift register is not cleared or altered). This
bit will return to a logic 0 after clearing the FIFO. FCR[0] FIFO enable.
logic 0= disable the transmit and receive FIFO (normal default
condition)
logic 1= enable the transmit and receive FIFO
NXP Semiconductors SC16C754B
5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs
7.4 Line Control Register (LCR)This register controls the data communication format. The word length, number of stop
bits, and parity type are selected by writing the appropriate bits to the LCR. Table12
shows the line control register bit settings.
Table 12. Line control register bits description LCR[7] Divisor latch enable.
logic 0= divisor latch disabled (normal default condition)
logic 1= divisor latch enabled LCR[6] Break control bit. When enabled, the Break control bit causes a break
condition to be transmitted (the TX output is forced to a logic 0 state). This
condition exists until disabled by setting LCR[6] to a logic0.
logic 0= no TX break condition (normal default condition)
logic 1= forces the transmitter output (TX) to a logic 0 to alert the
communication terminal to a line break condition LCR[5] Set parity. LCR[5] selects the forced parity format (if LCR[3]=1).
logic0= parity is not forced (normal default condition)
LCR[5]= logic 1
and LCR[4]= logic 0: parity bit is forced to a logic 1 for
the transmit and receive data
LCR[5]= logic 1
and LCR[4]= logic 1: parity bit is forced to a logic 0 for
the transmit and receive data LCR[4] Parity type select.
logic 0= odd parity is generated (if LCR[3]=1)
logic 1= even parity is generated (if LCR[3]=1) LCR[3] Parity enable.
logic 0= no parity (normal default condition)
logic 1= a parity bit is generated during transmission and the receiver
checks for received parity LCR[2] Number of stop bits. Specifies the number of stop bits.= 1 stop bit (word length= 5, 6, 7, 8)= 1.5 stop bits (word length=5)= 2 stop bits (word length= 6, 7, 8)
1:0 LCR[1:0] Word length bits 1, 0. These two bits specify the word length to be
transmitted or received.
00 —5 bits
01 —6 bits
10 —7 bits
11 —8 bits
NXP Semiconductors SC16C754B
5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs
7.5 Line Status Register (LSR)Table 13 shows the line status register bit settings.
When the LSR is read, LSR[4:2] reflect the error bits (BI, FE, PE) of the character at the
top of the RX FIFO (next character to be read). The LSR[4:2] registers do not physically
exist, as the data read from the RX FIFO is output directly onto the output data bus,
DI[4:2], when the LSR is read. Therefore, errors in a character are identified by reading
the LSR and then reading the RHR.
LSR[7] is set when there is an error anywhere in the RX FIFO, and is cleared only when
there are no more errors remaining in the FIFO.
Reading the LSR does not causean incrementof the RX FIFO read pointer. The RX FIFO
read pointer is incremented by reading the RHR.
Table 13. Line status register bits description LSR[7] FIFO data error.
logic 0= no error (normal default condition)
logic1=at least one parity error, framing error,or break indicationisin the
receiver FIFO. This bit is cleared when no more errors are present in the
FIFO. LSR[6] THR and TSR empty. This bit is the Transmit Empty indicator.
logic 0= transmitter hold
and shift registers are not emptylogic 1= transmitter hold
and shift registers are empty LSR[5] THR empty. This bit is the Transmit Holding Register Empty indicator.
logic 0=T ransmit Hold Register is
not emptylogic 1=T ransmit Hold Register is empty. The processor can now load up
to 64 bytes of data into the THR if the TX FIFO is enabled. LSR[4] Break interrupt.
logic0= no break condition (normal default condition)
logic1= a break condition occurred and associated byte is 00, that is, was LOW for one character time frame LSR[3] Framing error.
logic0=no framing errorin data being read from RX FIFO (normal default
condition)
logic1= framing error occurred in data being read from RX FIFO, that is,
received data did not have a valid stop bit LSR[2] Parity error.
logic 0= no parity error (normal default condition)
logic 1= parity error in data being read from RX FIFO LSR[1] Overrun error.
logic 0 = no overrun error (normal default condition)
logic 1= overrun error has occurred LSR[0] Data in receiver.
logic 0 = no data in receive FIFO (normal default condition)
logic 1= at least one character in the RX FIFO
