SC16C752BIBS ,5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOsFeatures■ Dual channel■ Pin compatible with SC16C2550 with additional enhancements■ Up to 5 Mbit/s ..
SC16C754BIA68 ,5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs
SC16C754BIA68 ,5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOsFeaturesn 4 channel UARTn 5 V, 3.3 V and 2.5 V operationn Pin compatible with SC16C654IA68, TL16C75 ..
SC16C754BIB80 ,5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOsBlock diagramSC16C754BTRANSMIT TRANSMITFIFO SHIFT TXA to TXDREGISTERS REGISTERD0 to D7 DATA BUSIOR ..
SC16C754BIB80 ,5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs
SC16C754BIBM ,5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOsLimiting values”.SC16C754BNXP Semiconductors5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64 ..
SDB20S30 ,Silicon Carbide Schottky DiodeSDP20S30Preliminary dataSDB20S30Silicon Carbide Schottky Diode
SC16C752BIBS
5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs
SC16C752BV , 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with
64-byte FIFOs
Rev. 03 — 14 December 2004 Product data DescriptionThe SC16C752B is a dual universal asynchronous receiver/transmitter (UART) with
64-byte FIFOs, automatic hardware/software flow control, and data rates up to Mbit/s (3.3 V and 5 V). The SC16C752B offers enhanced features. It has a
transmission control register (TCR) that stores receiver FIFO threshold levels to
start/stop transmission during hardware and software flow control. With the FIFO
RDY register, the software gets the status of TXRDY/RXRDY for all four ports in one
access. On-chip status registers provide the user with error indications, operational
status, and modem interface control. System interrupts may be tailored to meet user
requirements. An internal loop-back capability allows on-board diagnostics.
The UART transmits data, senttoit over the peripheral 8-bit bus,on the TX signal and
receives characterson the RX signal. Characters canbe programmedtobe5,6,7,or bits. The UART has a 64-byte receive FIFO and transmit FIFO and can be
programmed to interrupt at different trigger levels. The UART generates its own
desired baud rate based upon a programmable divisor and its input clock. It can
transmit even, odd, or no parity and 1, 1.5, or 2 stop bits. The receiver can detect
break, idle, or framing errors, FIFO overflow, and parity errors. The transmitter can
detect FIFO underflow. The UART also contains a software interface for modem
control operations, and has software flow control and hardware flow control
capabilities.
The SC16C752B is available in plastic LQFP48 and HVQFN32 packages.
Features Dual channel Pin compatible with SC16C2550 with additional enhancements Up to 5 Mbit/s baud rate (at 3.3 V and 5 V; at 2.5 V maximum baud rate is Mbit/s) 64-byte transmit FIFO 64-byte receive FIFO with error flags Programmable and selectable transmit and receive FIFO trigger levels for DMA
and interrupt generation Software/hardware flow control Programmable Xon/Xoff characters Programmable auto-RTS and auto-CTS Optional data flow resume by Xon any character DMA signalling capability for both received and transmitted data Supports 5 V, 3.3 V and 2.5 V operation5 V tolerant inputs
Philips Semiconductors SC16C752B V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs Software selectable baud rate generator Prescaler provides additional divide-by-4 function Industrial temperature range (−40 °C to +85 °C) Pin and software compatible with SC16C752, TL16C752 Fast databus access time Programmable sleep mode Programmable serial interface characteristics 5, 6, 7, or 8-bit characters Even, odd, or no parity bit generation and detection 1, 1.5, or 2 stop bit generation False start bit detection Complete status reporting capabilities in both normal and sleep mode Line break generation and detection Internal test and loop-back capabilities Fully prioritized interrupt system controls Modem control functions (CTS, RTS, DSR, DTR, RI, and CD).
Ordering information
Table 1: Ordering informationSC16C752BIB48 LQFP48 plastic low profile quad flat package; 48 leads; body 7×7× 1.4 mm SOT313-2
SC16C752BIBS HVQFN32 plastic thermal enhanced very thin quad flat package; no leads; terminals; body 5×5× 0.85 mm
SOT617-1
Philips Semiconductors SC16C752B V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs Block diagram
Philips Semiconductors SC16C752B V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs Pinning information
5.1 Pinning
Philips Semiconductors SC16C752B V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs
5.2 Pin description
Table 2: Pin description
Philips Semiconductors SC16C752B V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs
Table 2: Pin description…continued
Philips Semiconductors SC16C752B V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs Functional descriptionThe SC16C752B UART is pin-compatible with the SC16C2550 UART. It provides
more enhanced features. All additional features are provided through a special
enhanced feature register.
The UART will perform serial-to-parallel conversionon data characters received from
peripheral devicesor modems, and parallel-to-parallel conversionon data characters
transmitted by the processor. The complete status of each channel of the
SC16C752B UART can be read at any time during functional operation by the
processor.
The SC16C752B can be placed in an alternate mode (FIFO mode) relieving the
processor of excessive software overhead by buffering received/transmitted
characters. Both the receiver and transmitter FIFOs can store up to 64 bytes
(including three additional bitsof error status per bytefor the receiver FIFO) and have
selectableor programmable trigger levels. Primary outputs RXRDY and TXRDY allow
signalling of DMA transfers.
The SC16C752B has selectable hardware flow control and software flow control.
Hardware flow control significantly reduces software overhead and increases system
efficiencyby automatically controlling serial data flow using the RTS output and CTS
input signals. Software flow control automatically controls data flow by using
programmable Xon/Xoff characters.
The UART includes a programmable baud rate generator that can divide the timing
reference clock input by a divisor between 1 and (216− 1).
6.1 Trigger levelsThe SC16C752B provides independent selectable and programmable trigger levels
for both receiver and transmitter DMA and interrupt generation. After reset, both
transmitter and receiver FIFOs are disabled and so, in effect, the trigger level is the
default valueof one byte. The selectable trigger levels are available via the FCR. The
programmable trigger levels are available via the TLR.
6.2 Hardware flow controlHardware flow control is comprised of Auto-CTS and Auto-RTS. Auto-CTS and
Auto-RTS can be enabled/disabled independently by programming EFR[7:6].
With Auto-CTS, CTS must be active before the UART can transmit data.
Auto-RTS only activates the RTS output when there is enough room in the FIFO to
receive data and de-activates the RTS output when the RX FIFO is sufficiently full.
The halt and resume trigger levels in the TCR determine the levels at which RTS is
activated/deactivated.
If both Auto-CTS and Auto-RTS are enabled, when RTS is connected to CTS, data
transmission does not occur unless the receiver FIFO has empty space. Thus,
overrun errors are eliminated during hardware flow control. If not enabled, overrun
Philips Semiconductors SC16C752B V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs
6.2.1 Auto-RTSAuto-RTS data flow control originates in the receiver block (see Figure 1 “Block
diagram.” on page 3). Figure 5 shows RTS functional timing. The receiver FIFO
trigger levels used in Auto-RTS are stored in the TCR. RTS is active if the RX FIFO
level is below the halt trigger level in TCR[3:0]. When the receiver FIFO halt trigger
level is reached, RTS is deasserted. The sending device (e.g., another UART) may
sendan additional byte after the trigger levelis reached (assuming the sending UART
has another byte to send) because it may not recognize the deassertion of RTS until
it has begun sending the additional byte. RTS is automatically reasserted once the
receiver FIFO reaches the resume trigger level programmed via TCR[7:4]. This
reassertion allows the sending device to resume transmission.
Philips Semiconductors SC16C752B V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs
6.2.2 Auto-CTSThe transmitter circuitry checks CTS before sending the next data byte. When CTSis
active, the transmitter sends the next byte. T o stop the transmitter from sending the
following byte, CTS must be deasserted before the middle of the last stop bit that is
currently being sent. The auto-CTS function reduces interrupts to the host system.
When flow control is enabled, CTS level changes do not trigger host interrupts
because the device automatically controlsits own transmitter. Without auto-CTS, the
transmitter sends any data present in the transmit FIFO and a receiver overrun error
may result.
6.3 Software flow controlSoftware flow control is enabled through the enhanced feature register and the
modem control register. Different combinations of software flow control can be
enabled by setting different combinations of EFR[3:0]. Table 3 shows software flow
control options.
Table 3: Software flow control options (EFR[0:3]) 0 X X no transmit flow control 0 X X transmit Xon1, Xoff1 1 X X transmit Xon2, Xoff2 1 X X transmit Xon1, Xon2, Xoff1, Xoff2 X 0 0 no receive flow control X 1 0 receiver compared Xon1, Xoff1 X 0 1 receiver compares Xon2, Xoff2
1011transmit Xon1, Xoff1
receiver compares Xon1 and Xon2, Xoff1 and Xoff2
0111transmit Xon2, Xoff2
receiver compares Xon1 and Xon2, Xoff1 and Xoff2
1111transmit Xon1, Xon2, Xoff1, Xoff2
receiver compares Xon1 and Xon2, Xoff1 and Xoff2
Philips Semiconductors SC16C752B V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOsThere are two other enhanced features relating to software flow control:
Xon Any function (MCR[5]): Operation will resume after receiving any characterafter recognizing the Xoff character. It is possible that an Xon1 character is
recognized as an Xon Any character, which could cause an Xon2 character to be
written to the RX FIFO.
Special character (EFR[5]): Incoming datais comparedto Xoff2. Detectionof the
special character sets the Xoff interrupt (IIR[4]) but does not halt transmission. The
Xoff interruptis clearedbya readof the IIR. The special characteris transferredto
the RX FIFO.
6.3.1 RXWhen software flow control operation is enabled, the SC16C752B will compare
incoming data with Xoff1,2 programmed characters(in certain cases, Xoff1 and Xoff2
must be received sequentially). When the correct Xoff character are received,
transmission is halted after completing transmission of the current character. Xoff
detection also sets IIR[4] (if enabled via IER[5]) and causes INT to go HIGH.
To resume transmission, an Xon1,2 character must be received (in certain cases
Xon1 and Xon2 mustbe received sequentially). When the correct Xon characters are
received, IIR[4] is cleared, and the Xoff interrupt disappears.
6.3.2 TXXoff1/2 characteris transmitted when the RX FIFO has passed the HALT trigger level
programmed in TCR[3:0].
Xon1/2 character is transmitted when the RX FIFO reaches the RESUME trigger
level programmed in TCR[7:4].
The transmission of Xoff/Xon(s) follows the exact same protocol as transmission of ordinary byte from the FIFO. This means that evenif the word lengthis settobe5,
6, or 7 characters, then the 5, 6, or 7 least significant bits of Xoff1,2/Xon1,2 will be
transmitted. (Note that the transmission of 5, 6, or 7 bits of a character is seldom
done, but this functionality is included to maintain compatibility with earlier designs.)
It is assumed that software flow control and hardware flow control will never be
enabled simultaneously. Figure 7 shows an example of software flow control.
Philips Semiconductors SC16C752B V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs
6.3.3 Software flow control example
Assumptions: UART1 is transmitting a large text file to UART2. Both UARTs are
using software flow control with single character Xoff (0F) and Xon (0D) tokens. Both
have Xoff threshold (TCR[3:0]=F) setto 60, and Xon threshold (TCR[7:4]=8) setto
32. Both have the interrupt receive threshold (TLR[7:4]= D) set to 52.
UART 1 begins transmission and sends 52 characters, at which point UART2 will
generate an interrupt to its processor to service the RCV FIFO, but assume the
interrupt latency is fairly long. UART1 will continue sending characters until a total of
60 characters have been sent. At this time, UART2 will transmit a 0F to UART1,
informing UART1to halt transmission. UART1 will likely send the61st character while
UART2 is sending the Xoff character. Now UART2 is serviced and the processor
reads enough data out of the RX FIFO that the level drops to 32. UART2 will now
send a 0D to UART1, informing UART1 to resume transmission.
Philips Semiconductors SC16C752B V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs
6.4 ResetTable 4 summarizes the state of register after reset.
[1] Registers DLL, DLH, SPR, Xon1, Xon2, Xoff1, Xoff2 are not reset by the top-level reset signal
RESET, i.e., they hold their initialization values during reset.
Table 5 summarizes the state of registers after reset.
Table 4: Register reset functionsInterrupt enable register RESET All bits cleared.
Interrupt identification register RESET Bit 0 is set. All other bits cleared.
FIFO control register RESET All bits cleared.
Line control register RESET Reset to 00011101 (1D hex).
Modem control register RESET All bits cleared.
Line status register RESET Bits 5 and 6 set. All other bits cleared.
Modem status register RESET Bits 0-3 cleared. Bits 4-7 input signals.
Enhanced feature register RESET All bits cleared.
Receiver holding register RESET Pointer logic cleared.
Transmitter holding register RESET Pointer logic cleared.
Transmission control register RESET All bits cleared.
Trigger level register RESET All bits cleared.
Table 5: Signal RESET functions RESET high
RTS RESET high
DTR RESET high
RXRDY RESET high
TXRDY RESET low
Philips Semiconductors SC16C752B V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs
6.5 InterruptsThe SC16C752B has interrupt generation and prioritization (six prioritized levels of
interrupts) capability. The interrupt enable register (IER) enables eachof thesix types
of interrupts and the INT signal in response to an interrupt generation. The IER can
also disable the interrupt system by clearing bits 0-3, 5-7. When an interrupt is
generated, the IIR indicates that an interrupt is pending and provides the type of
interrupt through IIR[5;0]. Table 6 summarizes the interrupt control functions.
It is important to note that for the framing error, parity error, and break conditions,
LSR[7] generates the interrupt. LSR[7] is set when there is an error anywhere in the FIFO, and is cleared only when there are no more errors remaining in the FIFO.
LSR[4:2] always represent the error statusfor the received characterat the topof the FIFO. Reading the RX FIFO updates LSR[4:2] to the appropriate status for the
new character at the top of the FIFO. If the RX FIFO is empty, then LSR[4:2] are all
zeros.
For the Xoff interrupt, if an Xoff flow character detection caused the interrupt, the
interrupt is cleared by an Xon flow character detection. If a special character
detection caused the interrupt, the interrupt is cleared by a read of the LSR.
Table 6: Interrupt control functions000001 None none none none
000110 1 receiver line status OE, FE, PE, or BI errors occur in
characters in the RX FIFO
FE, PE, BI: all erroneous
characters are read from the FIFO.
OE: read LSR
001100 2 RX time-out stale data in RX FIFO read RHR
000100 2 RHR interrupt DRDY (data ready)
(FIFO disable)
RX FIFO above trigger level
(FIFO enable)
read RHR
000010 3 THR interrupt TFE (THR empty)
(FIFO disable) FIFO passes above trigger level
(FIFO enable)
read IIR
or a write to the THR000000 4 modem status MSR[3:0]=0 read MSR
010000 5 Xoff interrupt receive Xoff character(s)/special
character
receive Xon character(s)/Read of
IIR
100000 6 CTS, RTS RTSpinor CTSpin change state from
active (LOW) to inactive (HIGH)
read IIR
Philips Semiconductors SC16C752B V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs
6.5.1 Interrupt mode operation interrupt mode(if anybitof IER[3:0]is1) the processoris informedof the statusof
the receiver and transmitter by an interrupt signal, INT . Therefore, it is not necessary
to continuously poll the line status register (LSR) to see if any interrupt needs to be
serviced. Figure 8 shows interrupt mode operation.
6.5.2 Polled mode operationIn polled mode (IER[3:0]= 0000) the status of the receiver and transmitter can be
checked by polling the line status register (LSR). This mode is an alternative to the
FIFO interrupt mode of operation where the status of the receiver and transmitter is
automatically known by means of interrupts sent to the CPU. Figure 9 shows FIFO
polled mode operation.
Philips Semiconductors SC16C752B V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs
6.6 DMA operationThere are two modes of DMA operation, DMA mode 0 or DMA mode 1, selected by
FCR[3].
In DMA mode 0 or FIFO disable (FCR[0]= 0) DMA occurs in single character
transfers. In DMA mode 1, multi-character (or block) DMA transfers are managed to
relieve the processor for longer periods of time.
6.6.1 Single DMA transfers (DMA mode 0/FIFO disable)Figure 10 shows TXRDY and RXRDY in DMA mode 0/FIFO disable.
Transmitter: When empty, the TXRDY signal becomes active. TXRDY willgo inactive
after one character has been loaded into it.
Receiver: RXRDY is active when there is at least one character in the FIFO. It
becomes inactive when the receiver is empty.
Philips Semiconductors SC16C752B V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs
6.6.2 Block DMA transfers (DMA mode1)Figure 11 shows TXRDY and RXRDY in DMA mode1.
Transmitter: TXRDY is active when there is a trigger level number of spaces
available. It becomes inactive when the FIFO is full.
Receiver: RXRDY becomes active when the trigger level has been reached,or when
a time-out interrupt occurs. It will go inactive when the FIFO is empty or an error in
the RX FIFO is flagged by LSR[7].
6.7 Sleep modeSleep mode is an enhanced feature of the SC16C752B UART. It is enabled when
EFR[4], the enhanced functions bit, is set
and when IER[4] is set. Sleep mode isentered when:
The serial data input line, RX, is idle (see Section 6.8 “Break and time-out
conditions”).
The TX FIFO and TX shift register are empty.
There are no interrupts pending except THR and time-out interrupts.
Remark: Sleep mode will
not be entered if there is data in the RX FIFO. sleep mode, the UART clock and baud rate clock are stopped. Since most registers
are clocked using these clocks, the power consumptionis greatly reduced. The UART
will wake up when any change is detected on the RX line, when there is any change
in the state of the modem input pins, or if data is written to the TX FIFO.
Remark: Writingto the divisor latches, DLL and DLH,to set the baud clock, must not
be done during sleep mode. Therefore, it is advisable to disable sleep mode using
IER[4] before writing to DLL or DLH.
Philips Semiconductors SC16C752B V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs
6.8 Break and time-out conditionsAn RX idle condition is detected when the receiver line, RX, has been HIGH for character time. The receiver line is sampled midway through each bit.
When a break condition occurs, the TX line is pulled LOW. A break condition is
activated by setting LCR[6].
6.9 Programmable baud rate generatorThe SC16C752B UART contains a programmable baud generator that takes any
clock input and divides it by a divisor in the range between 1 and (216− 1). An
additional divide-by-4 prescaler is also available and can be selected by MCR[7], as
shownin Figure 12. The output frequencyof the baud rate generatoris 16× the baud
rate. The formula for the divisor is:
Where:
prescaler= 1, when MCR[7] is set to 0 after reset (divide-by-1 clock selected)
prescaler= 4, when MCR[7] is set to 1 after reset (divide-by-4 clock selected).
Remark: The default value of prescaler after reset is divide-by-1.
Figure 12 shows the internal prescaler and baud rate generator circuitry.
DLL and DLH mustbe writtentoin orderto program the baud rate. DLL and DLH are
the least significant and most significant byteof the baud rate divisor.If DLL and DLH
are both zero, the UART is effectively disabled, as no baud clock will be generated.
Remark: The programmable baud rate generator is provided to select both the
transmit and receive clock rates.
Table 7 and Table 8 show the baud rate and divisor correlation for crystal with
frequency 1.8432 MHz and 3.072 MHz, respectively.
divisor
XTAL1 crystal input frequency
prescaler ---------------------------------------------------------------------------
desired baud rate 16× () ---------------------------------------------------------------------------------=
Philips Semiconductors SC16C752B V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs
Table 7: Baud rates using a 1.8432 MHz crystal 2304 1536
110 1047 0.026
134.5 857 0.058
150 768
300 384
600 192
1200 96
1800 64
2000 58 0.69
2400 48
3600 32
4800 24
7200 16
9600 12
19200 6
38400 3
56000 2 2.86
Table 8: Baud rates using a 3.072 MHz crystal 2304 2560
110 1745 0.026
134.5 1428 0.034
150 1280
300 640
600 320
1200 160
1800 107 0.312
2000 96
2400 80
3600 53 0.628
4800 40
7200 27 1.23
9600 20
19200 10
38400 5
Philips Semiconductors SC16C752B V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs Register descriptionsEach register is selected using address lines A0, A1, A2, and in some cases, bits
from other registers. The programming combinationsfor register selection are shown Table9.
[1] MCR[7] can only be modified when EFR[4] is set.
[2] Accessed by a combination of address pins and register bits.
[3] Accessible only when LCR[7]is logic1.
[4] Accessible only when LCR is set to 10111111 (xBF).
[5] Accessible only when EFR[4]= 1 and MCR[6]= 1, i.e., EFR[4] and MCR[6] are read/write enables.
Table 9: Register map - read/write properties 0 0 receive holding register (RHR) transmit holding register (THR) 0 1 interrupt enable register (IER) interrupt enable register 1 0 interrupt identification register (IIR) FIFO control register (FCR) 1 1 line control register (LCR) line control register 0 0 modem control register (MCR)[1] modem control register[1] 0 1 line status register (LSR) 1 0 modem status register (MSR) 1 1 scratchpad register (SPR) scratchpad register 0 0 divisor latch LSB (DLL)[2],[3] divisor latch LSB[2],[3] 0 1 divisor latch MSB (DLH)[2],[3] divisor latch MSB[2],[3] 1 0 enhanced feature register (EFR)[2],[4] enhanced feature register[2],[4] 0 0 Xon1 word[2],[4] Xon1 word[2],[4] 0 1 Xon2 word[2],[4] Xon2 word[2],[4] 1 0 Xoff1 word[2],[4] Xoff1 word[2],[4] 1 1 Xoff2 word[2],[4] Xoff2 word[2],[4] 1 0 transmission control register (TCR)[2],[5] transmission control register [2],[5] 1 1 trigger level register (TLR) [2],[5] trigger level register[2],[5] 1 1 FIFO ready register[2],[6]
Philips Semiconductors SC16C752B V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOsTable 10 lists and describes the SC16C752B internal registers.
Table 10: SC16C752B internal registersShaded bits are only accessible when EFR[4] is set.
General Register Set[1]
Special Register Set[3]
Enhanced Register Set[4]
Philips Semiconductors SC16C752B V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs[3] The Special Register set is accessible only when LCR[7] is set to a logic 1.
[4] Enhanced Feature Register; Xon-1,2 and Xoff-1,2 are accessible only when LCR is set to ‘BFHex’.
Remark: Refer to the notes under Table 9 for more register access information.
7.1 Receiver holding register (RHR)The receiver section consists of the receiver holding register (RHR) and the receiver
shift register (RSR). The RHR is actually a 64-byte FIFO. The RSR receives serial
data from the RX terminal. The data is converted to parallel data and moved to the
RHR. The receiver section is controlled by the line control register. If the FIFO is
disabled, location zero of the FIFO is used to store the characters.
Remark: In this case, characters are overwritten if overflow occurs.
If overflow occurs, characters are lost. The RHR also stores the error status bits
associated with each character.
7.2 Transmit holding register (THR)The transmitter section consists of the transmit holding register (THR) and the
transmit shift register (TSR). The THR is actually a 64-byte FIFO. The THR receives
data and shifts it into the TSR, where it is converted to serial data and moved out on
the TX terminal. If the FIFO is disabled, the FIFO is still used to store the byte.
Characters are lost if overflow occurs.
Philips Semiconductors SC16C752B V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs
7.3 FIFO control register (FCR)This is a write-only register that is used for enabling the FIFOs, clearing the FIFOs,
setting transmitter and receiver trigger levels, and selecting the type of DMA
signalling. Table 11 shows FIFO control register bit settings.
Table 11: FIFO Control Register bits description7:6 FCR[7]
(MSB),
FCR[6]
(LSB)
RCVR trigger. Sets the trigger level for the RX FIFO.
00 - 8 characters
01 - 16 characters
10 - 56 characters
11 - 60 characters
5:4 FCR[5]
(MSB),
FCR[4]
(LSB)
TX trigger. Sets the trigger level for the TX FIFO.
00 - 8 spaces
01 - 16 spaces
10 - 32 spaces
11 - 56 spaces
FCR[5:4] can only be modified and enabled when EFR[4] is set. This is
because the transmit trigger level is regarded as an enhanced function. FCR[3] DMA mode select.
Logic 0= Set DMA mode ‘0’
Logic 1= Set DMA mode ‘1’ FCR[2] Reset TX FIFO.
Logic 0= No FIFO transmit reset (normal default condition).
Logic 1= Clears the contents of the transmit FIFO and resets the
FIFO counter logic (the transmit shift register is not cleared or
altered). This bit will return to a logic 0 after clearing the FIFO. FCR[1] Reset RX FIFO.
Logic 0= No FIFO receive reset (normal default condition).
Logic1= Clears the contentsof the receive FIFO and resetsthe FIFO
counter logic (the receive shift register is not cleared or altered). This
bit will return to a logic 0 after clearing the FIFO. FCR[0] FIFO enable.
Logic 0= Disable the transmit and receive FIFO (normal default
condition).
Logic 1= Enable the transmit and receive FIFO.
Philips Semiconductors SC16C752B V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs
7.4 Line control register (LCR)This register controls the data communication format. The word length, number of
stop bits, and parity type are selected by writing the appropriate bits to the LCR.
Table 12 shows the line control register bit settings.
Table 12: Line Control Register bits description LCR[7] Divisor latch enable.
Logic 0= Divisor latch disabled (normal default condition).
Logic 1= Divisor latch enabled. LCR[6] Break control bit. When enabled, the Break control bit causes a break
condition to be transmitted (the TX output is forced to a logic 0 state).
This condition exists until disabled by setting LCR[6] to a logic0.
Logic 0= no TX break condition (normal default condition).
Logic 1= forces the transmitter output (TX) to a logic 0 to alert the
communication terminal to a line break condition. LCR[5] Set parity. LCR[5] selects the forced parity format (if LCR[3]=1).
Logic0= parity is not forced (normal default condition).
LCR[5]= logic1 and LCR[4]= logic0: paritybitis forcedtoa logical1
for the transmit and receive data.
LCR[5]= logic1 and LCR[4]= logic1: paritybitis forcedtoa logical0
for the transmit and receive data. LCR[4] Parity type select.
Logic 0= ODD Parity is generated (if LCR[3]=1).
Logic 1= EVEN Parity is generated (if LCR[3]=1). LCR[3] Parity enable.
Logic 0= no parity (normal default condition).
Logic 1= a parity bit is generated during transmission and the
receiver checks for received parity. LCR[2] Number of Stop bits. Specifies the number of stop bits.
0 - 1 stop bit (word length= 5, 6, 7, 8)
1 - 1.5 stop bits (word length=5)= 2 stop bits (word length= 6, 7, 8)
1:0 LCR[1:0] Word length bits 1, 0. These two bits specify the word length to be
transmitted or received.
00 - 5 bits
01 - 6 bits
10 - 7 bits
11 - 8 bits
Philips Semiconductors SC16C752B V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs
7.5 Line status register (LSR)Table 13 shows the line status register bit settings.
When the LSR is read, LSR[4:2] reflect the error bits (BI, FE, PE) of the character at
the top of the RX FIFO (next character to be read). The LSR[4:2] registers do not
physically exist, as the data read from the RX FIFO is output directly onto the output
data bus, DI[4:2], when the LSRis read. Therefore, errorsina character are identified
by reading the LSR and then reading the RHR.
LSR[7] is set when there is an error anywhere in the RX FIFO, and is cleared only
when there are no more errors remaining in the FIFO.
Reading the LSR does not cause an increment of the RX FIFO read pointer. The
Table 13: Line Status Register bits description LSR[7] FIFO data error.
Logic 0= No error (normal default condition).
Logic 1= At least one parity error, framing error, or break indication is
in the receiver FIFO. This bit is cleared when no more errors are
present in the FIFO. LSR[6] THR and TSR empty. This bit is the Transmit Empty indicator.
Logic 0= Transmitter hold
and shift registers are not empty.Logic 1= Transmitter hold
and shift registers are empty. LSR[5] THR empty. This bit is the Transmit Holding Register Empty indicator.
Logic 0= Transmit hold register is
not empty.Logic 1= Transmit hold register is empty. The processor can now load
up to 64 bytes of data into the THR if the TX FIFO is enabled. LSR[4] Break interrupt.
Logic0= No break condition (normal default condition).
Logic1=A break condition occurred and associated byte is 00, i.e., was LOW for one character time frame. LSR[3] Framing error.
Logic0= No framing error in data being read from RX FIFO (normal
default condition).
Logic1=Framing error occurredin data being read fromRX FIFO, i.e.,
received data did not have a valid stop bit. LSR[2] Parity error.
Logic 0= No parity error (normal default condition).
Logic 1= Parity error in data being read from RX FIFO. LSR[1] Overrun error.
Logic 0 = No overrun error (normal default condition).
Logic 1= Overrun error has occurred. LSR[0] Data in receiver.
Logic 0 = No data in receive FIFO (normal default condition).
Logic 1= At least one character in the RX FIFO.
