SC16C654BIA68 ,5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.), with 64-byte FIFOs and infrared (IrDA) encoder/decoderFeatures■ 4 channel UART■ 5 V, 3.3 V and 2.5 V operation■ Industrial temperature range (- 40 °C to ..
SC16C654BIA68 ,5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.), with 64-byte FIFOs and infrared (IrDA) encoder/decoderFeatures■ 4 channel UART■ 5 V, 3.3 V and 2.5 V operation■ Industrial temperature range (- 40 °C to ..
SC16C654BIB64 ,SC16C654B/654DB; 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs and infrared (IrDA) encoder/decoderGeneral descriptionThe SC16C654B/654DB is a Quad Universal Asynchronous Receiver and Transmitter(QU ..
SC16C654BIBM ,5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.), with 64-byte FIFOs and infrared (IrDA) encoder/decoderfeatures arethe 64-byte receive and transmit FIFOs, automatic hardware or software flow control andi ..
SC16C654BIEC , 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.), with 64-byte FIFOs and infrared (IrDA) encoder/decoder
SC16C654DBIB64 ,5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.), with 64-byte FIFOs and infrared (IrDA) encoder/decoderSC16C654B/654DB5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.), with 64-byteFIFOs and infrared (IrD ..
SDB10150PI , DUAL COMMON CATHODE SCHOTTKY RECTIFIER
SDB102 , 1 Amp Single Phase Glass Passivated Bridge Rectifier 50 to 1000 Volts
SDB103 , 1 Amp Single Phase Glass Passivated Bridge Rectifier 50 to 1000 Volts
SDB103-TP , 1.0 Amp Single Phase Bridge Rectifier 50 to 1000 Volts
SDB104 , 1 Amp Single Phase Glass Passivated Bridge Rectifier 50 to 1000 Volts
SDB104 , 1 Amp Single Phase Glass Passivated Bridge Rectifier 50 to 1000 Volts
SC16C654BIA68
SC16C654B/654DB; 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs and infrared (IrDA) encoder/decoder
General descriptionThe SC16C654B/654DB is a 4-channel Universal Asynchronous Receiver and
Transmitter (QUART) used for serial data communications. Its principal function is to
convert parallel data into serial data and vice versa. The UART can handle serial data
rates up to 5 Mbit/s. It comes with an Intel® or Motorola® interface.
The SC16C654B/654DB is pin compatible with the ST16C654 and TL16C754 and it will
power-up to be functionally equivalent to the 16C454. Programming of control registers
enables the added featuresof the SC16C654B/654DB. Someof these added features are
the 64-byte receive and transmit FIFOs, automatic hardware or software flow control and
infrared encoding/decoding. The selectable auto-flow control feature significantly reduces
software overload and increases system efficiency while in FIFO mode by automatically
controlling serial data flow using RTS output and CTS input signals. The
SC16C654B/654DB also provides DMA mode data transfers through FIFO trigger levels
and the TXRDY and RXRDY signals. On-board status registers provide the user with error
indications, operational status, and modem interface control. System interrupts may be
tailored to meet user requirements. An internal loop-back capability allows on-board
diagnostics.
The SC16C654B/654DB operates at 5 V, 3.3 V and 2.5 V, and the industrial temperature
range, and is available in plastic PLCC68 and LQFP64 packages.
Features 4 channel UART5V , 3.3 V and 2.5 V operation Industrial temperature range (−40 °C to +85 °C) SC16C654B is pin and software compatible with the industry-standard
ST16C454/554, ST16C654, ST68C454/554, TL16C554 SC16C654DB is pin and software compatible with ST16C654D, and software
compatible with ST16C454/554, ST68C454/554, TL16C554 Up to 5 Mbit/s data rate at 5 V and 3.3 V and 3 Mbit/s at 2.5V5 V tolerant inputs 64-byte transmit FIFO 64-byte receive FIFO with error flags Automatic software (Xon/Xoff)/hardware (RTS/CTS) flow control Programmable Xon/Xoff characters Software selectable Baud Rate Generator Four selectable Receive and T ransmit FIFO interrupt trigger levels
SC16C654B/654DB
5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.), with 64-byte
FIFOs and infrared (IrDA) encoder/decoder
Philips Semiconductors SC16C654B/654DB Standard modem interface or infrared IrDA encoder/decoder interface Sleep mode Standard asynchronous error and framing bits (Start, Stop, and Parity Overrun Break) Transmit, Receive, Line Status, and Data Set interrupts independently controlled Fully programmable character formatting: 5, 6, 7, or 8-bit characters Even, Odd, or No Parity formats 1, 11 ⁄2, or 2-stop bit Baud generation (DC to 5 Mbit/s) False start-bit detection Complete status reporting capabilities 3-state output TTL drive capabilities for bi-directional data bus and control bus Line break generation and detection Internal diagnostic capabilities: Loop-back controls for communications link fault isolation Prioritized interrupt system controls Modem control functions (CTS, RTS, DSR, DTR, RI, CD).
Ordering information
Table 1: Ordering informationSC16C654BIA68 PLCC68 plastic leaded chip carrier; 68 leads SOT188-2
SC16C654BIB64 LQFP64 plastic low profile quad flat package; 64 leads; body 10×10× 1.4 mm SOT314-2
SC16C654DBIB64 LQFP64 plastic low profile quad flat package; 64 leads; body 10×10× 1.4 mm SOT314-2
Philips Semiconductors SC16C654B/654DB Block diagram
Philips Semiconductors SC16C654B/654DB
Philips Semiconductors SC16C654B/654DB Pinning information
5.1 Pinning
Philips Semiconductors SC16C654B/654DB
Philips Semiconductors SC16C654B/654DB
5.2 Pin description
Table 2: Pin description
Philips Semiconductors SC16C654B/654DB
Table 2: Pin description …continued
Philips Semiconductors SC16C654B/654DB
Table 2: Pin description …continued
Philips Semiconductors SC16C654B/654DB
Table 2: Pin description …continued
Philips Semiconductors SC16C654B/654DB Functional descriptionThe SC16C654B/654DB provides serial asynchronous receive data synchronization,
parallel-to-serial and serial-to-parallel data conversions for both the transmitter and
receiver sections. These functions are necessaryfor converting the serial data stream into
parallel data that is required with digital data systems. Synchronization for the serial data
stream is accomplished by adding start and stop bits to the transmit data to form a data
character. Data integrity is insured by attaching a parity bit to the data character. The
paritybitis checkedby the receiverfor any transmissionbit errors. The electronic circuitry
to provide all these functions is fairly complex, especially when manufactured on a single
integrated silicon chip. The SC16C654B/654DB represents such an integration with
greatly enhanced features. The SC16C654B/654DB is fabricated with an advanced
CMOS process to achieve low drain power and high speed requirements.
The SC16C654B/654DB is an upward solution that provides 64 bytes of transmit and
receive FIFO memory, insteadof16 bytes providedin the 16C554,or nonein the 16C454.
The SC16C654B/654DB is designed to work with high speed modems and shared
network environments that require fast data processing time. Increased performance is
realized in the SC16C654B/654DB by the larger transmit and receive FIFOs. This allows
the external processorto handle more networking tasks withina given time. For example,
the SC16C554 with a 16-byte FIFO unloads 16 bytes of receive data in 1.53 ms. (This
example uses a character length of 11 bits, including start/stop bits at 115.2 kbit/s.) This
means the external CPU will have to service the receive FIFO at 1.53 ms intervals.
However, with the 64-byte FIFOin the SC16C654B/654DB, the data buffer will not require
unloading/loadingfor 6.1 ms. This increases the service interval, giving the external CPU
additional time for other applications and reducing the overall UART interrupt servicing
time. In addition, the four selectable levels of FIFO trigger interrupt and automatic
hardware/software flow control is uniquely provided for maximum data throughput
performance, especially when operatingina multi-channel environment. The combination
of the above greatly reduces the bandwidth requirement of the external controlling CPU,
increases performance, and reduces power consumption.
The SC16C654B/654DB combines the package interface modes of the 16C454/554 and
68C454/554 series on a single integrated chip. The 16 mode interface is designed to
operate with the Intel-type of microprocessor bus, while the 68 mode is intended to
operate with Motorola and other popular microprocessors. Following a reset, the
SC16C654B/654DB is downward compatible with the 16C454/554 or the 68C454/554,
dependent on the state of the interface mode selection pin, 16/68.
The SC16C654B/654DB is capable of operation to 1.5 Mbit/s with a 24 MHz crystal and
up to 5 Mbit/s with an external clock input (at 3.3 V and 5 V; at 2.5 V the max speed is Mbit/s). With a crystal of 14.7464 MHz, and through a software option, the user can
select data rates up to 460.8 kbit/s or 921.6 kbit/s, 8 times faster than the 16C554.
The rich feature set of the SC16C654B/654DB is available through internal registers.
Automatic hardware/software flow control, selectable transmit and receive FIFO trigger
levels, selectable TX and RX baud rates, infrared encoder/decoder interface, modem
interface controls, and a sleep mode are all standard features. MCR[5] provides a facility
for turning off (Xon) software flow control with any incoming (RX) character. In the mode, INTSEL and MCR[3] can be configured to provide a software controlled or
continuous interrupt capability. Dueto pin limitationsof the 64-pin package, this featureis
Philips Semiconductors SC16C654B/654DBoffered by two different LQFP64 packages. The SC16C654D operates in the continuous
interrupt enable mode by bonding INTSEL to VCC internally. The SC16C654 operates in
conjunction with MCR[3] by bonding INTSEL to GND internally.
The PLCC68 SC16C654B package offers a clock select pin to allow system/board
designers to preset the default baud rate table. The CLKSEL pin selects the 1× or 4×
pre-scalable baud rate generator table during initialization, but canbe overridden following
initialization by MCR[7].
6.1 Interface optionsTwo user interface modes are selectablefor the PLCC68 package. These interface modes
are designatedas the ‘16 mode’ and the ‘68 mode’. This nomenclature correspondsto the
early 16C454/554 and 68C454/554 package interfaces respectively.
6.2 The 16 mode interfaceThe 16 mode configures the package interface pins for connection as a standard series (Intel) device and operates similar to the standard CPU interface available on
the 16C454/554. In the 16 mode (pin 16/68= logic 1), each UART is selected with
individual chip select (CSx) pins, as shown in Table3.
6.3 The 68 mode interfaceThe 68 mode configures the package interface pins for connection with Motorola, and
other popular microprocessor bus types. The interface operates similar to the
68C454/554. In this mode, the SC16C654B/654DB decodes two additional addresses,
A3-A4, to select one of the four UART ports. The A[3:4] address decode function is used
only when in the 68 mode (16/68= logic 0), and is shown inT able4.
Table 3: Serial port channel selection, 16 mode interface1111 none
0111A
1011B
1101C
1110D
Table 4: Serial port channel selection, 68 mode interface n/a n/a none
000A
001B
010C
011D
Philips Semiconductors SC16C654B/654DB
6.4 Internal registersThe SC16C654B/654DB provides 17 internal registers for monitoring and control. These
registers are shown in Table 5. Twelve registers are similar to those already available in
the standard 16C554. These registers function as data holding registers (THR/RHR),
interrupt status and control registers (IER/ISR), a FIFO control register (FCR), line status
and control registers (LCR/LSR), modem status and control registers (MCR/MSR),
programmable data rate (clock) control registers (DLL/DLM), and a user accessible
scratchpad register (SPR). Beyond the general 16C554 features and capabilities, the
SC16C654B/654DB offers an enhanced feature register set (EFR, Xon/Xoff1-2) that
provides on-board hardware/software flow control. Register functions are more fully
described in the following paragraphs.
[1] These registers are accessible only when LCR[7] is a logic0.
[2] These registers are accessible only when LCR[7] is a logic1.
[3] Enhanced Feature Register, Xon1, 2 and Xoff1, 2 are accessible only when the LCR is set to ‘BFh’.
6.5 FIFO operationThe 64-byte transmit and receive data FIFOs are enabled by the FIFO Control Register
(FCR)bit0. With SC16C554 devices, the user can set the receive trigger level, but not the
transmit trigger level. The SC16C654B/654DB provides independent trigger levelsfor both
receiver and transmitter. To remain compatible with SC16C554, the transmit interrupt
trigger level is set to 8 following a reset. It should be noted that the user can set the
transmit trigger levelsby writingto the FCR register, but activation will not take place until
EFR[4]is settoa logic1. The receiver FIFO section includesa time-out functionto ensure
data is delivered to the external CPU. An interrupt is generated whenever the Receive
Table 5: Internal registers decoding
General register set (THR/RHR, IER/ISR, MCR/MSR, FCR, LSR, SPR)[1] 0 0 Receive Holding Register Transmit Holding Register 0 1 Interrupt Enable Register Interrupt Enable Register 1 0 Interrupt Status Register FIFO Control Register 1 1 Line Control Register Line Control Register 0 0 Modem Control Register Modem Control Register 0 1 Line Status Register n/a 1 0 Modem Status Register n/a 1 1 Scratchpad Register Scratchpad Register
Baud rate register set (DLL/DLM)[2] 0 0 LSB of Divisor Latch LSB of Divisor Latch 0 1 MSB of Divisor Latch MSB of Divisor Latch
Enhanced register set (EFR, Xon/off 1-2)[3] 1 0 Enhanced Feature Register Enhanced Feature Register 0 0 Xon1 word Xon1 word 0 1 Xon2 word Xon2 word 1 0 Xoff1 word Xoff1 word 1 1 Xoff2 word Xoff2 word
Philips Semiconductors SC16C654B/654DBHolding Register (RHR) has not been read following the loading of a character or the
receive trigger level has not been reached. (For a description of this timing, see Section
6.6 “Hardware flow control”.)
6.6 Hardware flow controlWhen automatic hardware flow control is enabled, the SC16C654B/654DB monitors the
CTS pin for a remote buffer overflow indication and controls the RTS pin for local buffer
overflows. Automatic hardware flow control is selected by setting EFR[6] (RTS) and
EFR[7] (CTS) to a logic 1. If CTS transitions from a logic 0 to a logic 1 indicating a flow
control request, ISR[5] will be set to a logic 1 (if enabled via IER[6,7]), and the
SC16C654B/654DB will suspend TX transmissions as soon as the stop bit of the
characterin processis shifted out.T ransmissionis resumed after the CTS input returnsto
a logic 0, indicating more data may be sent.
With the Auto RTS function enabled, an interrupt is generated when the receive FIFO
reaches the programmed trigger level. The RTS pin will not be forced to a logic1
(RTS off), until the receive FIFO reaches the next trigger level. However, the RTS pin will
return to a logic 0 after the data buffer (FIFO) is unloaded to the next trigger level below
the programmed trigger. However, under the above described conditions, the
SC16C654B/654DB will continue to accept data until the receive FIFO is full.
6.7 Software flow controlWhen software flow control is enabled, the SC16C654B/654DB compares one or two
sequential receive data characters with the programmed Xon/Xoff or Xoff1,2 character
value(s). If received character(s) match the programmed values, the SC16C654B/654DB
will halt transmission (TX) as soon as the current character(s) has completed
transmission. When a match occurs, the receive ready (if enabled via Xoff IER[5]) flags
will be set and the interrupt output pin (if receive interrupt is enabled) will be activated.
Following a suspension due to a match of the Xoff characters’ values, the
SC16C654B/654DB will monitor the receive data stream for a match to the Xon1,2
character value(s).Ifa matchis found, the SC16C654B/654DB will resume operation and
clear the flags (ISR[4]). The SC16C654B/654DB offers a special Xon mode via MCR[5].
The initialized default settingof MCR[5]isa logic0.In this state, Xoff and Xon will operate defined above. Setting MCR[5]toa logic1 setsa special operational modefor the Xon
function. In this case, Xoff operates normally, however, transmission (Xon) will resume
with the next character received, that is, a match is declared simply by the receipt of an
incoming (RX) character.
Reset initially sets the contents of the Xon/Xoff 8-bit flow control registers to a logic0.
Following reset, the user can write any Xon/Xoff value desired for software flow control.
Different conditions can be set to detect Xon/Xoff characters and suspend/resume
Table 6: RX trigger levels 8 16 0 16 56 8 56 60 16 60 60 56
Philips Semiconductors SC16C654B/654DBtransmissions. When double 8-bit Xon/Xoff characters are selected, the
SC16C654B/654DB compares two consecutive receive characters with two software flow
control 8-bit values (Xon1, Xon2, Xoff1, Xoff2) and controls TX transmissions accordingly.
Under the above described flow control mechanisms, flow control characters are not
placed (stacked) in the user accessible RX data buffer or FIFO. the event that the receive bufferis overfilling and flow control needstobe executed, the
SC16C654B/654DB automatically sends an Xoff message (when enabled) via the serial
TX output to the remote modem. The SC16C654B/654DB sends the Xoff1,2 characters soonas received data passes the programmed trigger level.To clear this condition, the
SC16C654B/654DB will transmit the programmed Xon1,2 characters as soon as receive
data drops below the programmed trigger level.
6.8 Special feature software flow controlA special feature is provided to detect an 8-bit character when EFR[5] is set. When 8-bit
characteris detected,it willbe placedon the user-accessible data stack along with normal
incoming RX data. This condition is selected in conjunction with EFR[0:3]. Note that
software flow control should be turned off when using this special mode by setting
EFR[0:3] to a logic0.
The SC16C654B/654DB compares each incoming receive character with Xoff2 data. If a
match exists, the received data will be transferred to the FIFO, and ISR[4] will be set to
indicate detection of a special character. Although the Internal Register T able (Table8)
shows each X-Register with eight bitsof character information, the actual numberof bitsis
dependenton the programmed word length. Line Control Register bits LCR[0:1] define the
number of character bits, that is, either 5 bits, 6 bits, 7 bits or 8 bits. The word length
selected by LCR[0:1] also determine the number of bits that will be used for the special
character comparison. Bit0in the X-registers corresponds with the LSBbitfor the receive
character.
6.9 Xon any feature special featureis providedto return the Xoff flow controlto the inactive state followingits
activation. In this mode, any RX character received will return the Xoff flow control to the
inactive state so that transmissions may be resumed with a remote buffer. This feature is
more fully defined in Section 6.7 “Software flow control”.
6.10 Hardware/software and time-out interruptsThree special interrupts have been added to monitor the hardware and software flow
control. The interrupts are enabled by IER[5:7]. Care must be taken when handling these
interrupts. Following a reset, the transmitter interrupt is enabled, the SC16C654B/654DB
will issuean interruptto indicate that the Transmit Holding Registeris empty. This interrupt
must be serviced prior to continuing operations. The LSR register provides the current
singular highest priority interrupt only.It couldbe noted that CTS and RTS interrupts have
lowest interrupt priority. A condition can exist where a higher priority interrupt may mask
the lower priority CTS/RTS interrupt(s). Only after servicing the higher pending interrupt
will the lower priority CTS/TRS interrupt(s)be reflectedin the status register. Servicing the
interrupt without investigating further interrupt conditions can result in data errors.
Philips Semiconductors SC16C654B/654DBWhen two interrupt conditions have the same priority, it is important to service these
interrupts correctly. Receive Data Ready and Receive Time Out have the same interrupt
priority (when enabled by IER[0]). The receiver issues an interrupt after the number of
characters have reached the programmed trigger level. In this case, the
SC16C654B/654DB FIFO may hold more characters than the programmed trigger level.
Following the removal of a data byte, the user should re-check LSR[0] for additional
characters. A Receive Time Out will not occur if the receive FIFO is empty. The time-out
counter is reset at the center of each stop bit received or each time the receive holding
register (RHR) is read. The actual time-out value is 4 character time.
In the 16 mode for the PLCC68 package, the system/board designer can optionally
provide software controlled 3-state interrupt operation. This is accomplished by INTSEL
and MCR[3]. When INTSEL interface pin is left open or made a logic 0, MCR[3] controls
the 3-state interrupt outputs, INTAto INTD. When INTSEL is a logic 1, MCR[3] has no
effect on the INTAto INTD outputs, and the package operates with interrupt outputs
enabled continuously.
6.11 Programmable baud rate generatorThe SC16C654B/654DB supports high speed modem technologies that have increased
input data rates by employing data compression schemes. For example, a 33.6 kbit/s
modem that employs data compression may require a 115.2 kbit/s input data rate. 128.0 kbit/s ISDN modem that supports data compression may needan input data rate
of 460.8 kbit/s.
A single baud rate generator is provided for the transmitter and receiver, allowing
independent TX/RX channel control. The programmable Baud Rate Generatoris capable
of accepting an input clock up to 80 MHz (for 3.3 V and 5 V operation), as required for
supportinga5 Mbit/s data rate. The SC16C654B/654DB canbe configuredfor internalor
external clock operation. For internal clock oscillator operation, an industry standard
microprocessor crystal (parallel resonant/22 pF to 33 pF load) is connected externally
between the XTAL1 and XTAL2 pins (see Figure 6). Alternatively,an external clock canbe
connected to the XTAL1 pin to clock the internal baud rate generator for standard or
custom rates (see Table 7).
The generator divides the input 16× clock by any divisor from 1 to 216− 1. The
SC16C654B/654DB divides the basic external clock by 16. Further division of this 16×
clock provides two table rates to support low and high data rate applications using the
same system design. After a hardware reset and during initialization, the
Philips Semiconductors SC16C654B/654DBSC16C654B/654DB sets the default baud rate table accordingto the stateof the CLKSEL
pin.A logic1on CLKSEL will set the1× clock default, whereas logic0 will set the4× clock
default table. Following the default clock rate selection during initialization, the rate tables
can be changed by the internal register MCR[7]. Setting MCR[7] to a logic 1 when
CLKSEL is a logic 1 provides an additional divide-by-4, whereas setting MCR[7] to a
logic 0 only divides by 1. (SeeT able 7 and Figure 7.) Customized baud rates can be
achievedby selecting the proper divisor valuesfor the MSB and LSB sectionsof baud rate
generator.
Programming the Baud Rate Generator Registers DLM (MSB) and DLL (LSB) provides a
user capabilityfor selecting the desired final baud rate. The examplein Table7 shows the
two selectable baud rate tables available when using a 7.3728 MHz crystal.
Table 7: Baud rate generator programming table using a 7.3728 MHz clock 200 2304 900 09 00
300 1200 384 180 01 80
600 2400 192 C0 00 C0
1200 4800 96 60 00 60
2400 9600 48 30 00 30
4800 19.2k 24 18 00 18
9600 38.4k 12 0C 00 0C
19.2k 76.8k 6 06 00 06
38.4k 153.6k 3 03 00 03
57.6k 230.4k 2 02 00 02
115.2k 460.8k 1 01 00 01
Philips Semiconductors SC16C654B/654DB
6.12 DMA operationThe SC16C654B/654DB FIFO trigger level provides additional flexibility to the user for
block mode operation. LSR[5:6] providean indication when the transmitteris emptyor has
an empty location(s). The user can optionally operate the transmit and receive FIFOs in
the DMA mode (FCR[3]). When the transmit and receive FIFOs are enabled and the DMA
mode is de-activated (DMA Mode 0), the SC16C654B/654DB activates the interrupt
output pin for each data transmit or receive operation. When DMA mode is activated
(DMA Mode 1), the user takes the advantage of block mode operation by loading or
unloading the FIFO in a block sequence determined by the preset trigger level. In this
mode, the SC16C654B/654DB sets the interrupt output pin when characters in the
transmit FIFOs are below the transmit trigger level,or the charactersin the receive FIFOs
are above the receive trigger level.
6.13 Sleep modeThe SC16C654B/654DB is designed to operate with low power consumption. A special
sleep mode is included to further reduce power consumption when the chip is not being
used. With EFR[4] and IER[4] enabled (set to a logic 1), the SC16C654B/654DB enters
the sleep mode, but resumes normal operation when a start bit is detected, a change of
state on any of the modem input pins RX, RI, CTS, DSR, CD, or a transmit data is
provided by the user. If the sleep mode is enabled and the SC16C654B/654DB is
awakened by one of the conditions described above, it will return to the sleep mode
automatically after the last character is transmitted or read by the user. In any case, the
sleep mode will not be entered while an interrupt(s) is pending. The SC16C654B/654DB
will stay in the sleep mode of operation until it is disabled by setting IER[4] to a logic0.
6.14 Loop-back modeThe internal loop-back capability allows on-board diagnostics.In the loop-back mode, the
normal modem interface pins are disconnected and reconfigured for loop-back internally.
MCR[0:3] register bits are used for controlling loop-back diagnostic testing. In the
loop-back mode, OP1 and OP2 in the MCR register (bits 2:3) control the modem RI and
CD inputs, respectively. MCR signals DTR and RTS (bits 0:1) are used to control the
modem DSR and CTS inputs, respectively. The transmitter output (TX) and the receiver
input (RX) are disconnected from their associated interface pins, and instead are
connected together internally (see Figure 8). The CTS, DSR, CD, and RI are
disconnected from their normal modem control input pins, and instead are connected
internally to RTS, DTR, OP2 and OP1. Loop-back test data is entered into the transmit
holding register via the user data bus interface, D[0:7]. The transmit UART serializes the
data and passes the serial datato the receive UART via the internal loop-back connection.
The receive UART converts the serial data back into parallel data that is then made
availableat the user data interface D[0:7]. The user optionally compares the received data
to the initial transmitted data for verifying error-free operation of the UART TX/RX circuits.
In this mode, the receiver and transmitter interrupts are fully operational. The Modem
Control Interrupts are also operational. However, the interrupts can only be read using
lower four bitsof the Modem Status Register (MSR[0:3]) insteadof the four Modem Status
Register bits 4:7. The interrupts are still controlled by the IER.
Philips Semiconductors SC16C654B/654DB
Philips Semiconductors SC16C654B/654DB Register descriptionsTable 8 details the assigned bit functions for the SC16C654B/654DB internal registers.
The assigned bit functions are more fully defined in Section 7.1 through Section 7.11.
[1] The value shown represents the register’s initialized HEX value; X= n/a.
[2] These registers are accessible only when LCR[7]=0.
[3] These bits are only accessible when EFR[4] is set.
[4] The Special Register set is accessible only when LCR[7] is set to a logic1.
[5] Enhanced Feature Register, Xon-1,2 and Xoff-1,2 are accessible only when LCR is set to ‘BFh’.
Table 8: SC16C654B/654DB internal registers
General Register Set[2]
Special Register Set[4]
Enhanced Register Set[5]
Philips Semiconductors SC16C654B/654DB
7.1 Transmit (THR) and Receive (RHR) Holding RegistersThe serial transmitter section consists of an 8-bit Transmit Hold Register (THR) and
Transmit Shift Register (TSR). The status of the THR is provided in the Line Status
Register (LSR). Writingto the THR transfers the contentsof the data bus (D7to D0)to the
THR, providing that the THRor TSRis empty. The THR empty flagin the LSR register will
be set to a logic 1 when the transmitter is empty or when data is transferred to the TSR.
Note that a write operation can be performed when the THR empty flag is set
(logic0= FIFO full; logic1= at least one FIFO location available).
The serial receive section also contains an 8-bit Receive Holding Register (RHR).
Receive data is removed from the SC16C654B/654DB and receive FIFO by reading the
RHR register. The receive section provides a mechanism to prevent false starts. On the
falling edge of a start or false start bit, an internal receiver counter starts counting clocks
at the 16× clock rate. After 71 ⁄2 clocks, the start bit time should be shifted to the center of
the start bit. At this time the start bit is sampled, and if it is still a logic 0 it is validated.
Evaluating the start bit in this manner prevents the receiver from assembling a false
character. Receiver status codes will be posted in the LSR.
7.2 Interrupt Enable Register (IER)The Interrupt Enable Register (IER) masks the interrupts from receiver ready, transmitter
empty, line status and modem status registers. These interrupts would normally be seen
on the INTAto INTD output pins in the 16 mode, or on wire-OR IRQ output pin in the mode.
Table 9: Interrupt Enable Register bits description IER[7] CTS interrupt.
Logic0= Disable the CTS interrupt (normal default condition).
Logic 1 = Enable the CTS interrupt. The SC16C654B/654DB issues an
interrupt when the CTS pin transitions from a logic 0 to a logic1. IER[6] RTS interrupt.
Logic 0 = Disable the RTS interrupt (normal default condition).
Logic 1 = Enable the RTS interrupt. The SC16C654B/654DB issues an
interrupt when the RTS pin transitions from a logic 0 to a logic1. IER[5] Xoff interrupt.
Logic 0 = Disable the software flow control, receive Xoff interrupt (normal
default condition).
Logic 1 = Enable the software flow control, receive Xoff interrupt. See
Section 6.7 “Software flow control” for details. IER[4] Sleep mode.
Logic 0 = Disable sleep mode (normal default condition).
Logic 1 = Enable sleep mode. See Section 6.13 “Sleep mode” for details. IER[3] Modem Status Interrupt.
Logic 0 = Disable the modem status register interrupt (normal default
condition).
Logic 1 = Enable the modem status register interrupt.
Philips Semiconductors SC16C654B/654DB
7.2.1 IER versus Receive FIFO interrupt mode operationWhen the receive FIFO (FCR[0]= logic 1), and receive interrupts (IER[0]= logic 1) are
enabled, the receive interrupts and register status will reflect the following:
The receive data available interrupts are issued to the external CPU when the FIFO
has reached the programmed trigger level. It will be cleared when the FIFO drops
below the programmed trigger level.
FIFO status will also be reflected in the user accessible ISR register when the FIFO
trigger levelis reached. Both the ISR register statusbit and the interrupt willbe cleared
when the FIFO drops below the trigger level.
The data ready bit (LSR[0]) is set as soon as a character is transferred from the shift
register to the receive FIFO. It is reset when the FIFO is empty.
7.2.2 IER versus Receive/Transmit FIFO polled mode operationWhen FCR[0]= logic 1, resetting IER[0:3] enables the SC16C654B/654DB in the FIFO
polled mode of operation. Since the receiver and transmitter have separate bits in the
LSR, either or both can be used in the polled mode by selecting respective transmit or
receive control bit(s).
LSR[0] will be a logic 1 as long as there is one byte in the receive FIFO.
LSR[1:4] will provide the type of errors encountered, if any.
LSR[5] will indicate when the transmit FIFO is empty.
LSR[6] will indicate when both the transmit FIFO and transmit shift register are empty.
LSR[7] will indicate any FIFO data errors. IER[2] Receive Line Status interrupt.
Logic0= Disable the receiver line status interrupt (normal default condition).
Logic 1 = Enable the receiver line status interrupt. IER[1] Transmit Holding Register interrupt. This interrupt will be issued whenever the
THR is empty, and is associated with LSR[1].
Logic 0 = Disable the transmitter empty interrupt (normal default condition).
Logic 1 = Enable the transmitter empty interrupt. IER[0] Receive Holding Register interrupt. This interrupt willbe issued when the FIFO
has reached the programmed trigger level, or is cleared when the FIFO drops
below the trigger level in the FIFO mode of operation.
Logic 0 = Disable the receiver ready interrupt (normal default condition).
Logic 1 = Enable the receiver ready interrupt.
Table 9: Interrupt Enable Register bits description …continued
Philips Semiconductors SC16C654B/654DB
7.3 FIFO Control Register (FCR)This register is used to enable the FIFOs, clear the FIFOs, set the transmit/receive FIFO
trigger levels, and select the DMA mode.
7.3.1 DMA mode
7.3.1.1 Mode 0 (FCR bit 3 = 0)Set and enable the interruptfor each single transmitor receive operation, andis similarto
the 16C454 mode. T ransmit Ready (TXRDY) will go to a logic 0 whenever an empty
transmit space is available in the Transmit Holding Register (THR). Receive Ready
(RXRDY) willgotoa logic0 whenever the Receive Holding Register (RHR)is loaded with
a character.
7.3.1.2 Mode 1 (FCR bit 3 = 1)Set and enable the interruptina block mode operation. The transmit interruptis set when
the transmit FIFOis below the programmed trigger level. TXRDY remainsa logic0as long
as one empty FIFO location is available. The receive interrupt is set when the receive
FIFO fills to the programmed trigger level. However, the FIFO continues to fill regardless
of the programmed level until the FIFO is full. RXRDY remains a logic 0 as long as the
FIFO fill level is above the programmed trigger level.
7.3.2 FIFO mode
Table 10: FIFO Control Register bits description7:6 FCR[7] (MSB),
FCR[6] (LSB)
RCVR trigger. These bits are usedto set the trigger levelfor the receive
FIFO interrupt.
An interrupt is generated when the number of characters in the FIFO
equals the programmed trigger level. However, the FIFO will continueto
be loaded until it is full. Refer to Table 11.
5:4 FCR[5] (MSB),
FCR[4] (LSB)
TX trigger.
These bits are used to set the trigger level for the transmit FIFO
interrupt. The SC16C654B/654DB will issue a transmit empty interrupt
whenthe numberof charactersin FIFO drops below the selected trigger
level. Refer to Table 12. FCR[3] DMA mode select.
Logic 0 = Set DMA mode ‘0’ (normal default condition).
Logic 1 = Set DMA mode ‘1’
Transmit operation in mode ‘0’: When the SC16C654B/654DB is inthe 16C450 mode (FIFOs disabled; FCR[0]= logic 0) or in the FIFO
mode (FIFOs enabled; FCR[0]= logic 1; FCR[3]= logic 0), and when
there areno charactersin the transmit FIFOor transmit holding register,
the TXRDYpin willbea logic0. Once active, the TXRDYpin willgotoa
logic 1 after the first character is loaded into the transmit holding
register.
Receive operation in mode ‘0’: When the SC16C654B/654DB is inmode ‘0’ (FCR[0]= logic 0), or in the FIFO mode (FCR[0]= logic1;
FCR[3]= logic0) and thereisat least one characterinthe receive FIFO,
the RXRDYpin willbea logic0. Once active, the RXRDY pin willgotoa
logic 1 when there are no more characters in the receiver.
Philips Semiconductors SC16C654B/654DB(cont.)
FCR[3]
(continued)
Transmit operation in mode ‘1’: When the SC16C654B/654DB is inFIFO mode (FCR[0]= logic1; FCR[3]= logic1), the TXRDY pinwillbea
logic1 whenthe transmit FIFOis completely full.Itwillbea logic0 when
the trigger level has been reached.
Receive operation in mode ‘1’: When the SC16C654B/654DB is inFIFO mode (FCR[0]= logic1; FCR[3]= logic1) and the trigger level has
been reached,ora Receive Time-Out has occurred, the RXRDYpin will
go to a logic 0. Once activated, it will go to a logic 1 after there are no
more characters in the FIFO. FCR[2] XMIT FIFO reset.
Logic 0 = No FIFO transmit reset (normal default condition).
Logic 1 = Clears the contents of the transmit FIFO and resets the
FIFO counter logic (the transmit shift registeris not clearedor altered).
This bit will return to a logic 0 after clearing the FIFO. FCR[1] RCVR FIFO reset.
Logic 0 = No FIFO receive reset (normal default condition).
Logic1= Clears the contentsofthe receive FIFO and resets the FIFO
counter logic (the receive shift register is not cleared or altered). This
bit will return to a logic 0 after clearing the FIFO. FCR[0] FIFO enable.
Logic 0 = Disable the transmit and receive FIFO (normal default
condition).
Logic 1 = Enable the transmit and receive FIFO.
This bit must be a
‘1’ when other FCR bits are written to, or they will not be
programmed.
Table 11: RX trigger levelsTable 12: TX trigger levels
Table 10: FIFO Control Register bits description …continued
Philips Semiconductors SC16C654B/654DB
7.4 Interrupt Status Register (ISR)The SC16C654B/654DB provides six levels of prioritized interrupts to minimize external
software interaction. The Interrupt Status Register (ISR) provides the user with six
interrupt status bits. Performing a read cycle on the ISR will provide the user with the
highest pending interrupt level to be serviced. No other interrupts are acknowledged until
the pending interrupt is serviced. Whenever the interrupt status register is read, the
interrupt status is cleared. However, it should be noted that only the current pending
interrupt is cleared by the read. A lower level interrupt may be seen after re-reading the
interrupt status bits. Table13 “Interrupt source” shows the data values (bits 0:5)for the six
prioritized interrupt levels and the interrupt sources associated with eachof these interrupt
levels.
Table 13: Interrupt source 000110 LSR (Receiver Line Status
Register) 000100 RXRDY (Receive Data
Ready) 001100 RXRDY (Receive Data
time-out) 000010 TXRDY (Transmitter Holding
Register Empty) 000000 MSR (Modem Status
Register) 010000 RXRDY (Received Xoff
signal) / Special character 100000CTS, RTS change of state
Table 14: Interrupt Status Register bits description7:6 ISR[7:6] FIFOs enabled. These bits are set to a logic 0 when the FIFO is not
being used. They are set to a logic 1 when the FIFOs are enabled.
Logic 0 or cleared = default condition.
5:4 ISR[5:4] INT priority bits 4:3. These bits are enabled when EFR[4] is set to a
logic 1. ISR[4] indicates that matching Xoff character(s) have been
detected. ISR[5] indicates that CTS, RTS have been generated. Note
that once set to a logic 1, the ISR[4] bit will stay a logic 1 until Xon
character(s) are received.
Logic 0 or cleared = default condition.
3:1 ISR[3:1] INT priority bits 2:0. These bits indicate the source for a pending
interrupt at interrupt priority levels 1, 2, and 3 (see Table 13).
Logic 0 or cleared = default condition. ISR[0] INT status.
Logic 0 = An interrupt is pending and the ISR contents may be used
as a pointer to the appropriate interrupt service routine.
Logic 1 = No interrupt pending (normal default condition).
