SC16C652BIBS ,5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.) with 32-byte FIFOs and infrared (IrDA) encoder/decoderfeatures may betailored by software to meet specific user requirements. An internal loop-back capabi ..
SC16C652BIBS ,5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.) with 32-byte FIFOs and infrared (IrDA) encoder/decoderGeneral descriptionThe SC16C652B is a 2 channel Universal Asynchronous Receiver and Transmitter(UAR ..
SC16C652IB48 ,Dual UART with 32 bytes of transmit and receive FIFOs
SC16C654BIA68 ,5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.), with 64-byte FIFOs and infrared (IrDA) encoder/decoderFeatures■ 4 channel UART■ 5 V, 3.3 V and 2.5 V operation■ Industrial temperature range (- 40 °C to ..
SC16C654BIA68 ,5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.), with 64-byte FIFOs and infrared (IrDA) encoder/decoderFeatures■ 4 channel UART■ 5 V, 3.3 V and 2.5 V operation■ Industrial temperature range (- 40 °C to ..
SC16C654BIB64 ,SC16C654B/654DB; 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs and infrared (IrDA) encoder/decoderGeneral descriptionThe SC16C654B/654DB is a Quad Universal Asynchronous Receiver and Transmitter(QU ..
SDB0530 , Schottky Barrier Diode
SDB0540 , Schottky Barrier Rectifier
SDB06S60 ,600V Silicon Carbide Ultrafast Schottky DiodeSDP06S60, SDB06S60SDT06S60Silicon Carbide Schottky Diode thinQ! SiC Schottky Diode• Worlds first 6 ..
SDB10150PI , DUAL COMMON CATHODE SCHOTTKY RECTIFIER
SDB102 , 1 Amp Single Phase Glass Passivated Bridge Rectifier 50 to 1000 Volts
SDB103 , 1 Amp Single Phase Glass Passivated Bridge Rectifier 50 to 1000 Volts
SC16C652BIB48-SC16C652BIBS
5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.) with 32-byte FIFOs and infrared (IrDA) encoder/decoder
General descriptionThe SC16C652B is a 2 channel Universal Asynchronous Receiver and Transmitter
(UART) used for serial data communications. Its principal function is to convert parallel
data into serial data and vice versa. The UART can handle serial data ratesupto5 Mbit/s.
The SC16C652Bis pin compatible with the SC16C2550.It will power-uptobe functionally
equivalent to the 16C2450. The SC16C652B provides enhanced UART functions with
32-byte FIFOs, modem control interface, DMA mode data transfer, and IrDA
encoder/decoder. The DMA mode data transfer is controlled by the FIFO trigger levels
and the TXRDY and RXRDY signals. On-board status registers provide the user with error
indications and operational status. System interrupts and modem control features maybe
tailored by software to meet specific user requirements. An internal loop-back capability
allows on-board diagnostics. Independent programmable baud rate generators are
provided to select transmit and receive baud rates.
The SC16C652B operates at 5V , 3.3 V and 2.5 V and the industrial temperature range,
and is available in plastic LQFP48 and very small (Micro-UART) HVQFN32 packages.
Features 2 channel UART5V , 3.3 V and 2.5 V operation5 V tolerant inputs Industrial temperature range (−40 °C to +85 °C) Pin and functionally compatible to 16C2450 in LQFP48 package, and software
compatible with industry standard 16C450, 16C550, and SC16C650 Up to 5 Mbit/s data rate at 5 V and 3.3 V, and 3 Mbit/s at 2.5V 32-byte transmit FIFO to reduce the bandwidth requirement of the external CPU 32-byte receive FIFO with error flags to reduce the bandwidth requirement of the
external CPU Independent transmit and receive UART control Four selectable Receive and T ransmit FIFO interrupt trigger levels Automatic software (Xon/Xoff) and hardware (RTS/CTS) flow control Programmable Xon/Xoff characters Software selectable baud rate generator Standard modem interface or infrared IrDA encoder/decoder interface Supports IrDA version 1.0 (up to 115.2 kbit/s) Sleep mode Standard asynchronous error and framing bits (Start, Stop, and Parity Overrun Break)
SC16C652B
5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.) with 32-byte
FIFOs and infrared (IrDA) encoder/decoder
Philips Semiconductors SC16C652B Transmit, Receive, Line Status, and Data Set interrupts independently controlled Fully programmable character formatting: 5-bit, 6-bit, 7-bit, or 8-bit characters Even, odd, or no-parity formats 1, 11 ⁄2, or 2-stop bit Baud generation (DC to 5 Mbit/s) False start-bit detection Complete status reporting capabilities 3-state output TTL drive capabilities for bi-directional data bus and control bus Line break generation and detection Internal diagnostic capabilities: Loop-back controls for communications link fault isolation Prioritized interrupt system controls Modem control functions (CTS, RTS, DSR, DTR, RI, CD)
Ordering information
Table 1: Ordering informationSC16C652BIB48 LQFP48 plastic low profile quad flat package; 48 leads; body 7×7× 1.4 mm SOT313-2
SC16C652BIBS HVQFN32 plastic thermal enhanced very thin quad flat package; no leads; terminals; body 5×5× 0.85 mm
SOT617-1
Philips Semiconductors SC16C652B Block diagram
Philips Semiconductors SC16C652B Pinning information
5.1 Pinning
Philips Semiconductors SC16C652B
5.2 Pin description
Table 2: Pin description 28 19 I
Address 0 select bit. Internal register address selection. 27 18 I
Address 1 select bit. Internal register address selection. 26 17 I
Address 2 select bit. Internal register address selection.CDA40 - I
Carrier Detect (active LOW). These inputs are associated with individual UARTchannels A through B. A logic 0 on this pin indicates that a carrier has been
detected by the modem for that channel.CDB 16 -
CSA 10 8 I
Chip Select A, B (active LOW). This function is associated with individualchannels, A through B. These pins enable data transfers between the user CPU
andthe SC16C652Bforthe channel(s) addressed. Individual UART sections(A,B)
are addressed by providing a logic 0 on the respective CSA, CSB pin.
CSB 11 9
CTSA 38 25 I
Clear to Send (active LOW). These inputs are associated with individual UARTchannels,A throughB.A logic0on the CTSpin indicatesthe modemor datasetis
ready to accept transmit data from the SC16C652B. Status can be tested by
reading MSR[4]. This pin has no effect on the UART’s transmit or receive
operation.
CTSB 23 16
DSRA 39 - I
Data Set Ready (active LOW). These inputs are associated with individual UART
channels, A through B. A logic 0 on this pin indicates the modem or data set is
powered-on and is ready for data exchange with the UART. This pin has no effect
on the UART’s transmit or receive operation.
DSRB 20 -
DTRA 34 - O
Data Terminal Ready (active LOW). These outputs are associated with individual
UART channels,A throughB.A logic0on thispin indicates that the SC16C652Bis
powered-on and ready. This pin can be controlled via the modem control register.
Writinga logic1to MCR[0] willset the DTR outputto logic0, enabling the modem.
This pin will be a logic 1 after writing a logic 0 to MCR[0], or after a reset. This pin
has no effect on the UART’s transmit or receive operation.
DTRB 35 - 44 27 I/O
Data bus (bi-directional). These pins are the 8-bit, 3-state data bus fortransferring informationtoor from the controlling CPU.D0is the least significantbit
and the first data bit in a transmit or receive serial data stream.D1 45 28 46 29 47 30 48 31 1 32 2 1 3 2
GND 17 13 I
Signal and power ground.INTA 30 21 O
Interrupt A, B (3-state). This function is associated with individual channelinterrupts, INTA, INTB. INTA, INTB are enabled when MCRbit3is settoa logic1,
interrupts are enabledinthe Interrupt Enable Register (IER), andis active whenan
interrupt condition exists. Interrupt conditions include: receiver errors, available
receiver buffer data, transmit buffer empty, or when a modem status flag is
detected.
INTB 29 20
IOR 19 14 I
Read strobe (active LOW strobe). A logic 0 transition on this pin will load thecontents of an internal register defined by address bits A0to A2 onto the
SC16C652B data bus (D0to D7) for access by external CPU.
Philips Semiconductors SC16C652BIOW15 12 I
Write strobe (active LOW strobe). A logic 0 transition on this pin will transfer the
contents of the data bus (D0to D7) from the external CPU to an internal register
that is defined by address bits A0to A2.
OP2A 32 22 O
Output 2 (user-defined). This function is associated with individual channels, Athrough B. The state at these pin(s) are defined by the user and through MCR
register bit 3. INTA, INTB are set to the active mode and OP2 to logic 0 when
MCR[3] is set to a logic 1. INTA, INTB are set to the 3-state mode and OP2 to a
logic1 when MCR[3]issettoa logic0 (see Table20 “Modem Control Register bits
description”, bit 3). Since these bits control both the INTA, INTB operation and
OP2 outputs, only one function should be used at one time, INT or OP2.
OP2B 9 7
RESET 36 24 I
Reset (active HIGH). A logic 1 on this pin will reset the internal registers and all
the outputs. The UART transmitter output and the receiver input will be disabled
during reset time. (See Section 7.11 “SC16C652B external reset condition” for
initialization details.)
RIA 41 - I
Ring Indicator (active LOW). These inputs are associated with individual UARTchannels, A through B. A logic 0 on this pin indicates the modem has received a
ringing signal from the telephone line. A logic 1 transition on this input pin will
generate an interrupt.
RIB 21 -
RTSA 33 23 O
Request to Send (active LOW). These outputs are associated with individualUART channels, A through B. A logic 0 on the RTS pin indicates the transmitter
has data ready and waitingto send. Writinga logic1inthe modem control register
MCR[1] will set this pin to a logic 0, indicating data is available. After a reset this
pin willbesettoa logic1. Thispin hasno effecton the UART’s transmitor receive
operation.
RTSB 22 15
RXA 5 4 I
Receive dataA,B. These inputs are associated with individual serial channel data
to the SC16C652B receive input circuits, A through B. The RX signal will be a
logic 1 during reset, idle (no data), or when the transmitter is disabled. During the
local loop-back mode, the RX inputpinis disabled andTX datais connectedtothe
UART RX input, internally.
RXB 4 3
RXRDYA31 - O
Receive Ready A, B (active LOW). This function provides the RX FIFO/RHR
status for individual receive channels (AtoB). RXRDYn is primarily intended for
monitoring DMA mode 1 transfers for the receive data FIFOs. A logic 0 indicates
there is a receive data to read/upload, that is, receive ready status with one or
more RX characters available in the FIFO/RHR. This pin is a logic 1 when the
FIFO/RHR is empty or when the programmed trigger level has not been reached.
This signal can also be used for single mode transfers (DMA mode 0).
RXRDYB 18 -
TXA 7 5 O
Transmit data A, B. These outputs are associated with individual serial transmitchannel data from the SC16C652B. The TX signal will be a logic 1 during reset,
idle (no data), or when the transmitter is disabled. During the local loop-back
mode, the TX output pin is disabled and TX data is internally connected to the
UART RX input.
TXB 8 6
TXRDYA43 - O
Transmit Ready A, B (active LOW). These outputs provide the TX FIFO/THR
status for individual transmit channels (AtoB). TXRDYn is primarily intended for
monitoring DMA mode 1 transfers for the transmit data FIFOs. An individual
channel’s TXRDYA, TXRDYB buffer ready status is indicated by logic 0, that is, at
lease one location is empty and available in the FIFO or THR. This pin goes to a
logic 1 (DMA mode 1) when there are no more empty locations in the FIFO or
THR. This signal can also be used for single mode transfers (DMA mode0).
TXRDYB 6 -
Table 2: Pin description …continued
Philips Semiconductors SC16C652B Functional descriptionThe SC16C652B provides serial asynchronous receive data synchronization,
parallel-to-serial and serial-to-parallel data conversions for both the transmitter and
receiver sections. These functions are necessaryfor converting the serial data stream into
parallel data that is required with digital data systems. Synchronization for the serial data
stream is accomplished by adding start and stop bits to the transmit data to form a data
character (character orientated protocol). Data integrityis insuredby attachinga paritybit
to the data character. The parity bit is checked by the receiver for any transmission bit
errors. The electronic circuitry to provide all these functions is fairly complex, especially
when manufactured on a single integrated silicon chip. The SC16C652B represents such
an integration with greatly enhanced features. The SC16C652B is fabricated with an
advanced CMOS process.
The SC16C652Bisan upward solution that providesa dual UART capability with32 bytes
of transmit and receive FIFO memory, instead of 16 bytes for the 16C2550 and none in
the 16C2450. The SC16C652Bis designedto work with high speed modems and shared
network environments that require fast data processing time. Increased performance is
realized in the SC16C652B by the transmit and receive FIFOs. This allows the external
processor to handle more networking tasks within a given time. In addition, the four
selectable receive and transmit FIFO trigger interrupt levels are uniquely provided for
maximum data throughput performance especially when operating in a multi-channel
environment. The FIFO memory greatly reduces the bandwidth requirement of the
external controlling CPU, increases performance, and reduces power consumption.
The SC16C652Bis capableof operationupto5 Mbit/s witha80 MHz clock. Witha crystal
or external clock input of 7.3728 MHz, the user can select data rates up to 460.8 kbit/s.
The rich feature set of the SC16C652B is available through internal registers. Selectable
receive and transmit FIFO trigger levels, selectable TX and RX baud rates, and modem
interface controls are all standard features. Following a power-on reset or an external
reset, the SC16C652B is software compatible with the previous generation, SC16C2550
and ST16C2450.
VCC 42 26 I
Power supply input.XTAL1 13 10 I
Crystal or external clock input. Functions as a crystal input or as an externalclock input. A crystal can be connected between this pin and XTAL2 to form an
internal oscillator circuit. This configuration requires an external 1 MΩ resistor
between the XT AL1 and XTAL2 pins. Alternatively, an external clock can be
connected to this pin to provide custom data rates (see Section 6.8
“Programmable baud rate generator”). See Figure4.
XTAL2 14 11 O
Output of the crystal oscillator or buffered clock. (See also XTAL1.) Crystaloscillator outputor buffered clock output. Shouldbeleft openifan external clockis
connected to XTAL1. For extended frequency operation, this pin should be tied to
VCC via a 2 kΩ resistor.
Table 2: Pin description …continued
Philips Semiconductors SC16C652B
6.1 UART A-B functionsThe UART provides the user with the capability to bi-directionally transfer information
between an external CPU, the SC16C652B package, and an external serial device. A
logic 0 on chip select pins CSA and/or CSB allows the user to configure, send data,
and/or receive data via UART channels A-B. Individual channel select functions are shown Table3.
6.2 Internal registersThe SC16C652B provides two sets of internal registers (A and B) consisting of registers each for monitoring and controlling the functions of each channel of the
UART. These registers are shownin Table4. The UART registers functionas data holding
registers (THR/RHR), interrupt status and control registers (IER/ISR), a FIFO Control
Register (FCR), line status and control registers (LCR/LSR), modem status and control
registers (MCR/MSR), programmable data rate (clock) control registers (DLL/DLM), anda
user accessible Scratchpad Register (SPR).
[1] These registers are accessible only when LCR[7] is a logic0.
[2] These registers are accessible only when LCR[7] is a logic1.
[3] Enhanced Feature Register, Xon1/Xon2 and Xoff1/Xoff2 are accessible only when the LCR is set to ‘BFh’.
Table 3: Serial port selectionCSA-CSB=1 none
CSA=0 UART channel A
CSB=0 UART channel B
Table 4: Internal registers decoding
General register set (THR/RHR, IER/ISR, MCR/MSR, FCR, LSR, SPR)[1] 0 0 Receive Holding Register Transmit Holding Register 0 1 Interrupt Enable Register Interrupt Enable Register 1 0 Interrupt Status Register FIFO Control Register 1 1 Line Control Register Line Control Register 0 0 Modem Control Register Modem Control Register 0 1 Line Status Register n/a 1 0 Modem Status Register n/a 1 1 Scratchpad Register Scratchpad Register
Baud rate register set (DLL/DLM)[2] 0 0 LSB of Divisor Latch LSB of Divisor Latch 0 1 MSB of Divisor Latch MSB of Divisor Latch
Enhanced register set (EFR, Xon1/Xon2, Xoff1/Xoff2)[3] 1 0 Enhanced Feature Register Enhanced Feature Register 0 0 Xon1 word Xon1 word 0 1 Xon2 word Xon2 word 1 0 Xoff1 word Xoff1 word 1 1 Xoff2 word Xoff2 word
Philips Semiconductors SC16C652B
6.3 FIFO operationThe 32-byte transmit and receive data FIFOs are enabled by the FIFO Control Register
bit 0 (FCR[0]). With 16C2550 devices, the user can set the receive trigger level, but not
the transmit trigger level. The SC16C652B provides independent trigger levels for both
receiver and transmitter. To remain compatible with SC16C2550, the transmit interrupt
trigger level is set to 16 following a reset. It should be noted that the user can set the
transmit trigger levels by writing to the FCR, but activation will not take place until EFR[4] settoa logic1. The receiver FIFO section includesa time-out functionto ensure datais
delivered to the external CPU. An interrupt is generated whenever the Receive Holding
Register (RHR) has not been read following the loading of a character or the receive
trigger level has not been reached.
6.4 Hardware flow controlWhen automatic hardware flow controlis enabled, the SC16C652B monitors the CTS pin
for a remote buffer overflow indication and controls the RTS pin for local buffer overflows.
Automatic hardware flow controlis selectedby setting EFR[6] (RTS) and EFR[7] (CTS)to
a logic 1. If CTS transitions from a logic 0 to a logic 1 indicating a flow control request,
ISR[5] will be set to a logic 1 (if enabled via IER[7:6]), and the SC16C652B will suspend
TX transmissions as soon as the stop bit of the character in process is shifted out.
Transmissionis resumed after the CTS input returnstoa logic0, indicating more data may
be sent.
With the Auto-RTS function enabled, an interrupt is generated when the receive FIFO
reaches the programmed trigger level. The RTS pin will not be forced to a logic 1 (RTS
off), until the receive FIFO reaches the next trigger level. However, the RTS pin will return
to a logic 0 after the data buffer (FIFO) is unloaded to the next trigger level below the
programmed trigger level. However, under the above described conditions, the
SC16C652B will continue to accept data until the receive FIFO is full.
6.5 Software flow controlWhen software flow control is enabled, the SC16C652B compares one or two sequential
receive data characters with the programmed Xon or Xoff character value(s). If received
character(s) match the programmed Xoff values, the SC16C652B will halt transmission
(TX) as soon as the current character(s) has completed transmission. When a match
occurs, the receive ready (if enabled via Xoff IER[5]) flags will be set and the interrupt
output pin(if receive interruptis enabled) willbe activated. Followinga suspension dueto
a match of the Xoff characters’ values, the SC16C652B will monitor the receive data
stream for a match to the Xon1/Xon2 character value(s). If a match is found, the
SC16C652B will resume operation and clear the flags (ISR[4]).
Table 5: Flow control mechanism 16 8 0 16 8 16 7 24 24 24 15 28 30 28 23
Philips Semiconductors SC16C652BReset initially sets the contents of the Xon/Xoff 8-bit flow control registers to a logic0.
Following reset, the user can write any Xon/Xoff value desired for software flow control.
Different conditions can be set to detect Xon/Xoff characters and suspend/resume
transmissions. When double 8-bit Xon/Xoff characters are selected, the SC16C652B
compares two consecutive receive characters with two software flow control 8-bit values
(Xon1, Xon2, Xoff1, Xoff2) and controls TX transmissions accordingly. Under the above
described flow control mechanisms, flow control characters are not placed (stacked)in the
user accessible RX data buffer or FIFO. When using a software flow control the Xon/Xoff
characters cannot be used for data transfer. the event that the receive bufferis overfilling and flow control needstobe executed, the
SC16C652B automatically sends an Xoff message (when enabled) via the serial TX
outputto the remote modem. The SC16C652B sends the Xoff1/Xoff2 charactersas soon
as received data passes the programmed trigger level. To clear this condition, the
SC16C652B will transmit the programmed Xon1/Xon2 charactersas soonas receive data
drops below the programmed trigger level.
6.6 Special feature software flow controlA special feature is provided to detect an 8-bit character when EFR[5] is set. When 8-bit
characteris detected,it willbe placedon the user-accessible data stack along with normal
incoming RX data. This condition is selected in conjunction with EFR[3:0]. Note that
software flow control should be turned off when using this special mode by setting
EFR[3:0] to a logic0.
The SC16C652B compares each incoming receive character with Xoff2 data. If a match
exists, the received data will be transferred to the FIFO, and ISR[4] will be set to indicate
detection of a special character. Although Table 9 “SC16C652B internal registers” shows
each X-Register with eight bits of character information, the actual number of bits is
dependenton the programmed word length. Line Control Register bits LCR[1:0] define the
number of character bits, that is, either 5 bits, 6 bits, 7 bits or 8 bits. The word length
selected by LCR[1:0] also determine the number of bits that will be used for the special
character comparison. Bit0in the X-registers corresponds with the LSBbitfor the receive
character.
6.7 Hardware/software and time-out interruptsThe interrupts are enabled by IER[3:0]. Care must be taken when handling these
interrupts. Following a reset, if Interrupt Enable Register (IER) bit1= 1, the SC16C652B
will issue a Transmit Holding Register interrupt. This interrupt must be serviced prior to
continuing operations. The ISR provides the current singular highest priority interrupt only.
It could be noted that CTS and RTS interrupts have lowest interrupt priority. A condition
can exist where a higher priority interrupt may mask the lower priority CTS/RTS
interrupt(s). Only after servicing the higher pending interrupt will the lower priority
CTS/RTS interrupt(s) be reflected in the status register. Servicing the interrupt without
investigating further interrupt conditions can result in data errors.
When two interrupt conditions have the same priority, it is important to service these
interrupts correctly. Receive Data Ready and Receive Time Out have the same interrupt
priority (when enabled by IER[0]). The receiver issues an interrupt after the number of
characters have reached the programmed trigger level. In this case, the SC16C652B
FIFO may hold more characters than the programmed trigger level. Following the removal
of a data byte, the user should re-check LSR[0] for additional characters. A Receive
Philips Semiconductors SC16C652BTime Out will not occur if the receive FIFO is empty. The time-out counter is reset at the
centerof each stopbit receivedor each time the Receive Holding Register (RHR)is read.
The actual time-out value is 4 character time, including data information length, start bit,
parity bit, and the size of stop bit, that is, 1×, 1.5×, or 2× bit times.
6.8 Programmable baud rate generatorThe SC16C652B supports high speed modem technologies that have increased input
data rates by employing data compression schemes. For example, a 33.6 kbit/s modem
that employs data compression may require a 115.2 kbit/s input data rate. A 128.0 kbit/s
ISDN modem that supports data compression may needan input data rateof 460.8 kbit/s.
The SC16C652B can support a standard data rate of 921.6 kbit/s.
A single baud rate generator is provided for the transmitter and receiver, allowing
independent TX/RX channel control. The programmable Baud Rate Generatoris capable
of operating with a frequency of up to 80 MHz. To obtain maximum data rate, it is
necessaryto use full rail swingon the clock input. The SC16C652B canbe configuredfor
internal or external clock operation. For internal clock oscillator operation, an industry
standard microprocessor crystal is connected externally between the XTAL1 and XTAL2
pins. Alternatively, an external clock can be connected to the XTAL1 pin to clock the
internal baud rate generator for standard or custom rates (seeT able 6).
The generator divides the input 16× clock by any divisor from 1 to (216− 1). The
SC16C652B divides the basic external clock by 16. The basic 16× clock provides table
rates to support standard and custom applications using the same system design. The
rate tableis configured via the DLL and DLM internal register functions. Customized baud
rates can be achieved by selecting the proper divisor values for the MSB and LSB
sections of baud rate generator.
Programming the baud rate generator registers DLM (MSB) and DLL (LSB) provides a
user capabilityfor selecting the desired final baud rate. The examplein Table6 shows the
selectable baud rate table available when using a 1.8432 MHz external clock input.
Philips Semiconductors SC16C652B
6.9 DMA operationThe SC16C652B FIFO trigger level provides additional flexibility to the user for block
mode operation. The user can optionally operate the transmit and receive FIFOs in the
DMA mode (FCR[3]). The DMA mode affects the state of the RXRDY and TXRDY output
pins.T able 7 andT able 8 show this.
6.10 Loop-back modeThe internal loop-back capability allows on-board diagnostics.In the loop-back mode, the
normal modem interface pins are disconnected and reconfigured for loop-back internally
(see Figure5). MCR[3:0] register bits are usedfor controlling loop-back diagnostic testing.
In the loop-back mode, the transmitter output (TX) and the receiver input (RX) are
disconnected from their associated interface pins, and instead are connected together
internally. The CTS, DSR, CD, andRI are disconnected from their normal modem control
inputs pins, and instead are connected internally to RTS, DTR, MCR[3] (OP2) and
Table 6: Baud rate generator programming table using a 1.8432 MHz clock 2304 900 09 00 1536 600 06 00
110 1047 417 04 17
150 768 300 03 00
300 384 180 01 80
600 192 C0 00 C0
1200 96 60 00 60
2400 48 30 00 30
3600 32 20 00 20
4800 24 18 00 18
7200 16 10 00 10
9600 12 0C 00 0C
19.2k 6 06 00 06
38.4k 3 03 00 03
57.6k 2 02 00 02
115.2k 1 01 00 01
Table 7: Effect of DMA mode on state of RXRDY pin= FIFO empty 0-to-1 transition when FIFO empties= at least 1 byte in FIFO 1-to-0 transition when FIFO reaches trigger level,or time-out occurs
Table 8: Effect of DMA mode on state of TXRDY pin= at least 1 byte in FIFO 0-to-1 transition when FIFO becomes full= FIFO empty 1-to-0 transition when FIFO goes below trigger level
Philips Semiconductors SC16C652BMCR[2] (OP1). Loop-back test data is entered into the transmit holding register via the
user data bus interface, D[7:0]. The transmit UART serializes the data and passes the
serial data to the receive UART via the internal loop-back connection. The receive UART
converts the serial data back into parallel data thatis then made availableat the user data
interface D[7:0]. The user optionally compares the received data to the initial transmitted
data for verifying error-free operation of the UART TX/RX circuits.
In this mode, the receiver and transmitter interrupts are fully operational. The modem
control interrupts are also operational.
Philips Semiconductors SC16C652B
6.11 Sleep modeSleep modeisan enhanced featureof the SC16C652B UART.Itis enabled when EFR[4],
the enhanced functions bit, is set
and when IER[4] of both channels are set. Sleep modeis entered when:
Modem input pins are not toggling.
The serial data input line, RX, is idle (logic HIGH).
The TX FIFO and TX shift register are empty.
There are no interrupts pending.
Remark: Sleep mode will
not be entered if there is data in the RX FIFO. Sleep mode, the UART clock and baud rate clock are stopped. Since most registers are
clocked using these clocks, the power consumption is greatly reduced.
Remark: Writing to the divisor latches, DLL and DLH, to set the baud clock, must not be
done during Sleep mode. Therefore, it is advisable to disable Sleep mode using IER[4]
before writing to DLL or DLH.
SC16C652B resumes normal operation by any of the following:
Receives a start bit on RXA/RXB pin.
Data is loaded into transmit FIFO.
A change of state on any of the modem input pins
If the device is awakened by one of the conditions described above, it will return to the
Sleep mode automatically after the last character is transmitted or read by the user. The
device will stay in Sleep mode until it is disabled by setting any channel’s IER bit 4 to a
logic0.
Philips Semiconductors SC16C652B Register descriptionsTable 9 details the assigned bit functions for the SC16C652B internal registers. The
assigned bit functions are more fully defined in Section 7.1 through Section 7.11.
[1] The value shown in represents the register’s initialized HEX value; X= not applicable.
[2] This bit is only accessible when EFR[4] is set.
[3] Accessible only when LCR[7] is logic0.
[4] Baud rate registers accessible only when LCR[7] is logic1.
[5] Enhanced Feature Register, Xon1/Xon2 and Xoff1/Xoff2 are accessible only when LCR is set to ‘BFh’.
Table 9: SC16C652B internal registers
General Register Set[3]
Special Register Set[4]
Enhanced Register Set[5]
Philips Semiconductors SC16C652B
7.1 Transmit (THR) and Receive (RHR) Holding RegistersThe serial transmitter section consists of an 8-bit Transmit Hold Register (THR) and
Transmit Shift Register (TSR). The status of the THR is provided in the Line Status
Register (LSR). Writingto the THR transfers the contentsof the data bus (D7to D0)to the
TSR and UART via the THR, providing that the THR is empty. The THR empty flag in the
LSR willbe settoa logic1 when the transmitteris emptyor when datais transferredto the
TSR. Note that a write operation can be performed when the THR empty flag is set
(logic0= at least one byte in FIFO/THR, logic1= FIFO/THR empty).
The serial receive section also contains an 8-bit Receive Holding Register (RHR) and a
Receive Serial Shift Register (RSR). Receive data is removed from the SC16C652B and
receive FIFO by reading the RHR. The receive section provides a mechanism to prevent
false starts. On the falling edge of a start or false start bit, an internal receiver counter
starts counting clocks at the 16× clock rate. After 71 ⁄2 clocks, the start bit time should be
shifted to the center of the start bit. At this time the start bit is sampled, and if it is still a
logic 0 it is validated. Evaluating the start bit in this manner prevents the receiver from
assembling a false character. Receiver status codes will be posted in the LSR.
7.2 Interrupt Enable Register (IER)The Interrupt Enable Register (IER) masks the interrupts from receiver ready, transmitter
empty, line status and modem status registers. These interrupts would normally be seen
on the INTA, INTB output pins.
Table 10: Interrupt Enable Register bits description IER[7] CTS interrupt.
logic0= disable the CTS interrupt (normal default condition)
logic1= enable the CTS interrupt. The SC16C652B issues an interrupt when
the CTS pin transitions from a logic 0 to a logic1. IER[6] RTS interrupt.
logic0= disable the RTS interrupt (normal default condition)
logic1= enable the RTS interrupt. The SC16C652B issues an interrupt when
the RTS pin transitions from a logic 0 to a logic1. IER[5] Xoff interrupt.
logic0= disable the software flow control, receive Xoff interrupt (normal
default condition)
logic1= enable the software flow control, receive Xoff interrupt. IER[4] Sleep mode.
logic0= disable Sleep mode (normal default condition)
logic1= enable Sleep mode IER[3] Modem Status Interrupt. This interrupt willbe issued whenever thereisa modem
status change as reflected in MSR[3:0].
logic0= disable the modem status register interrupt (normal default condition)
logic1= enable the modem status register interrupt IER[2] Receive Line Status interrupt. This interrupt will be issued whenever a receive
data error condition exists as reflected in LSR[4:1].
logic0= disable the receiver line status interrupt (normal default condition)
logic1= enable the receiver line status interrupt
Philips Semiconductors SC16C652B
7.2.1 IER versus Transmit/Receive FIFO interrupt mode operationWhen the receive FIFO (FCR[0]= logic 1), and receive interrupts (IER[0]= logic 1) are
enabled, the receive interrupts and register status will reflect the following:
The receive RXRDY interrupt (Level 2 ISR interrupt) is issued to the external CPU
when the receive FIFO has reached the programmed trigger level. It will be cleared
when the receive FIFO drops below the programmed trigger level.
Receive FIFO status will also be reflected in the user accessible ISR register when
the receive FIFO trigger level is reached. Both the ISR register receive status bit and
the interrupt will be cleared when the FIFO drops below the trigger level.
The receive data ready bit (LSR[0]) is set as soon as a character is transferred from
the shift register (RSR) to the receive FIFO. It is reset when the FIFO is empty.
When the Transmit FIFO and interrupts are enabled, an interrupt is generated when
the transmit FIFOis empty dueto the unloadingof the databy the TSR and UARTfor
transmission via the transmission media. The interruptis cleared eitherby reading the
ISR, or by loading the THR with new data characters.
7.2.2 IER versus Receive/Transmit FIFO polled mode operationWhen FCR[0]= logic 1, resetting IER[3:0] enables the SC16C652B in the FIFO polled
mode of operation. In this mode, interrupts are not generated and the user must poll the
LSR register for TX and/or RX data status. Since the receiver and transmitter have
separate bits in the LSR either or both can be used in the polled mode by selecting
respective transmit or receive control bit(s).
LSR[0] will be a logic 1 as long as there is one byte in the receive FIFO.
LSR[4:1] will provide the type of receive errors, or a receive break, if encountered.
LSR[5] will indicate when the transmit FIFO is empty.
LSR[6] will indicate when both the transmit FIFO and transmit shift register are empty.
LSR[7] will show if any FIFO data errors occurred. IER[1] Transmit Holding Register interrupt. In the 16C450 mode, this interrupt will be
issued whenever the THR is empty, and is associated with LSR[5]. In the FIFO
modes, this interrupt will be issued whenever the FIFO is empty.
logic0= disable the Transmit Holding Register Empty (TXRDY) interrupt
(normal default condition)
logic1= enable the TXRDY (ISR level 3) interrupt IER[0] Receive Holding Register.In the 16C450 mode, this interrupt willbe issued when
the RHR has data, or is cleared when the RHR is empty. In the FIFO mode, this
interrupt willbe issued when the FIFO has reached the programmed trigger level
or is cleared when the FIFO drops below the trigger level.
logic0= disable the receiver ready (ISR level 2, RXRDY) interrupt (normal
default condition)
logic1= enable the RXRDY (ISR level 2) interrupt
Table 10: Interrupt Enable Register bits description …continued
Philips Semiconductors SC16C652B
7.3 FIFO Control Register (FCR)This register is used to enable the FIFOs, clear the FIFOs, set the receive FIFO trigger
levels, and select the DMA mode.
7.3.1 DMA mode
7.3.1.1 Mode 0 (FCR bit 3=0)Set and enable the interruptfor each single transmitor receive operation, andis similarto
the 16C450 mode. Transmit Ready (TXRDY) willgotoa logic0 whenever the FIFO (THR, FIFOis not enabled)is empty. Receive Ready (RXRDY) willgotoa logic0 whenever the
Receive Holding Register (RHR) is loaded with a character.
7.3.1.2 Mode 1 (FCR bit 3=1)Set and enable the interruptina block mode operation. The transmit interruptis set when
the transmit FIFOis below the programmed trigger level. The receive interruptis set when
the receive FIFO fills to the programmed trigger level. However, the FIFO continues to fill
regardlessof the programmed level until the FIFOis full. RXRDY remainsa logic0as long
as the FIFO fill level is above the programmed trigger level.
7.3.2 FIFO mode
Table 11: FIFO Control Register bits description7:6 FCR[7:6] RCVR trigger. These bits are usedtoset the trigger levelfor the receive FIFO
interrupt.
An interrupt is generated when the number of characters in the FIFO equals
the programmed trigger level. However, the FIFO will continue to be loaded
until it is full. Refer to Table 12.
5:4 FCR[5:4] Logic 0 or cleared is the default condition; TX trigger level= 16.
These bits are used to set the trigger level for the transmit FIFO interrupt.
The SC16C652B will issue a transmit empty interrupt when the number of
characters in FIFO drops below the selected trigger level. Refer to Table 13. FCR[3] DMA mode select.
logic0= set DMA mode ‘0’ (normal default condition)
logic1= set DMA mode ‘1’
Transmit operation in mode ‘0’: When the SC16C652B is in the 16C450mode (FIFOs disabled; FCR[0]= logic 0) or in the FIFO mode (FIFOs
enabled; FCR[0]= logic 1; FCR[3]= logic 0), and when there are no
characters in the transmit FIFO or transmit holding register, the TXRDY pin
willbea logic0. Once active, the TXRDY pin willgotoa logic1 after the first
character is loaded into the transmit holding register.
Receive operationin mode ‘0’: When the SC16C652Bisin 16C450 mode,in the FIFO mode (FCR[0]= logic1; FCR[3]= logic0) and thereisat least
one character in the receive FIFO, the RXRDY pin will be a logic 0. Once
active, the RXRDY pinwillgotoa logic1 when there areno more characters
in the receiver.
Philips Semiconductors SC16C652B(cont.)
Transmit operation in mode ‘1’: When the SC16C652B is in FIFO mode(FCR[0]= logic1; FCR[3]= logic1), the TXRDYpinwillbea logic1 when the
transmit FIFO is completely full. It will be a logic 0 when the trigger level has
been reached.
Receive operation in mode ‘1’: When the SC16C652B is in FIFO mode(FCR[0]= logic 1; FCR[3]= logic 1) and the trigger level has been reached,
or a Receive Time-Out has occurred, the RXRDY pin will go to a logic0.
Once activated,it willgotoa logic1 after there areno more charactersinthe
FIFO. FCR[2] XMIT FIFO reset.
logic0= no FIFO transmit reset (normal default condition)
logic1= clears the contents of the transmit FIFO and resets the FIFO
counter logic (the transmit shift register is not cleared or altered). This bit
will return to a logic 0 after clearing the FIFO. FCR[1] RCVR FIFO reset.
logic0= no FIFO receive reset (normal default condition)
logic1= clears the contents of the receive FIFO and resets the FIFO
counter logic (the receive shift register is not cleared or altered). This bit
will return to a logic 0 after clearing the FIFO. FCR[0] FIFO enable.
logic0= disable the transmit and receive FIFO (normal default condition)
logic1= enable the transmit and receive FIFO.
This bit must be a ‘1’
when other FCR bits are written to, or they will not be programmed.
Table 12: RCVR trigger levelsTable 13: TX FIFO trigger levels
Table 11: FIFO Control Register bits description …continued
Philips Semiconductors SC16C652B
7.4 Interrupt Status Register (ISR)The SC16C652B provides six levelsof prioritized interruptsto minimize external software
interaction. The Interrupt Status Register (ISR) provides the user with six interrupt status
bits. Performing a read cycle on the ISR will provide the user with the highest pending
interrupt level to be serviced. No other interrupts are acknowledged until the pending
interrupt is serviced. A lower level interrupt may be seen after servicing the higher level
interrupt and re-reading the interrupt status bits. Table 14 “Interrupt source” shows the
data values (bits 5:0) for the six prioritized interrupt levels and the interrupt sources
associated with each of these interrupt levels.
Table 14: Interrupt source 0 00110 LSR (Receiver Line Status
Register) 0 00100 RXRDY (Received Data Ready) 0 01100 RXRDY (Receive Data time-out) 0 00010 TXRDY (Transmitter Holding
Register Empty) 0 00000 MSR (Modem Status Register) 0 10000 RXRDY (Received Xoff signal)/
Special character 1 00000CTS, RTS change of state
Table 15: Interrupt Status Register bits description7:6 ISR[7:6] FIFOs enabled. These bits are settoa logic0 when the FIFOs arenot being
used in the 16C450 mode. They are set to a logic 1 when the FIFOs are
enabled in the SC16C652B mode.
logic 0 or cleared= default condition
5:4 ISR[5:4] INT priority bits 4:3. These bits are enabled when EFR[4]is settoa logic1.
ISR[4] indicates that matching Xoff character(s) have been detected. ISR[5]
indicates that CTS, RTS have been generated. Note that once set to a
logic 1, the ISR[4] bit will stay a logic 1 until Xon character(s) are received.
logic 0 or cleared= default condition
3:1 ISR[3:1] INT priority bits 2:0. These bits indicate the sourcefora pending interruptat
interrupt priority levels 1, 2, and 3 (see Table 14).
logic 0 or cleared= default condition ISR[0] INT status.
logic0= an interrupt is pending and the ISR contents may be used as a
pointer to the appropriate interrupt service routine
logic1= no interrupt pending (normal default condition)
Philips Semiconductors SC16C652B
7.5 Line Control Register (LCR)The Line Control Register is used to specify the asynchronous data communication
format. The word length, the numberof stop bits, and the parity are selectedby writing the
appropriate bits in this register.
Table 16: Line Control Register bits description LCR[7] Divisor latch enable. The internal baud rate counter latch and Enhanced
Feature mode enable.
logic0 = divisor latch disabled (normal default condition)
logic1= divisor latch enabled LCR[6] Set break. When enabled, the Break controlbit causesa break conditionto
be transmitted (the TX output is forced to a logic 0 state). This condition
exists until disabled by setting LCR[6] to a logic0.
logic0= no TX break condition (normal default condition)
logic1= forces the transmitter output (TX) to a logic 0 for alerting the
remote receiver to a line break condition
5:3 LCR[5:3] Programs the parity conditions (see Table 17). LCR[2] Stop bits. The lengthof stopbitis specifiedby thisbitin conjunction withthe
programmed word length (see Table 18).
logic 0 or cleared= default condition
1:0 LCR[1:0] Word length bits 1, 0. These two bits specify the word length to be
transmitted or received (see Table 19).
logic 0 or cleared= default condition
Table 17: LCR[5:3] parity selection X 0 no parity 0 1 odd parity 1 1 even parity 0 1 forced parity ‘1’ 1 1 forced parity ‘0’
Table 18: LCR[2] stop bit length 5, 6, 7, 8 1 11⁄2 6, 7, 8 2
Table 19: LCR[1:0] word length 5 6 7 8
Philips Semiconductors SC16C652B
7.6 Modem Control Register (MCR)This register controls the interface with the modem or a peripheral device.
Table 20: Modem Control Register bits description MCR[7] Clock select
logic0 = divide-by-1 clock input
logic1= divide-by-4 clock input MCR[6] IR enable (see Figure 17).
logic 0 = enable the standard modem receive and transmit input/output
interface (normal default condition)
logic 1 = enable infrared IrDA receive and transmit inputs/outputs. While
in this mode, the TX/RX output/inputs are routed to the infrared
encoder/decoder. The data input and output levels will conform to the
IrDA infrared interface requirement. As such, while in this mode, the
infrared TX output will be a logic 0 during idle data conditions. MCR[5] Reserved; set to ‘0’. MCR[4] Loop-back. Enable the local loop-back mode (diagnostics).In this modethe
transmitter output (TX) and the receiver input (RX), CTS, DSR, CD, andRI
are disconnected from the SC16C652BI/O pins. Internally the modem data
and control pins are connected into a loop-back data configuration (see
Figure 5). In this mode, the receiver and transmitter interrupts remain fully
operational. The Modem Control Interrupts are also operational, but the
interrupts’ sources are switchedto the lower four bitsofthe Modem Control.
Interrupts continue to be controlled by the IER register.
logic0= disable Loop-back mode (normal default condition)
logic1= enable local Loop-back mode (diagnostics) MCR[3] OP2/INT enable
logic0= forces INT(A,B) outputsto the 3-state mode and sets OP2toa
logic 1 (normal default condition)
logic1= forces the INT(A,B) outputstothe active mode and sets OP2to
a logic0 MCR[2] (OP1). OP1A/OP1B are not available as an external signal in the
SC16C652B. This bit is instead used in the Loop-back mode only. In the
Loop-back mode, thisbitis usedto write the stateof the modemRI interface
signal. MCR[1] RTS
logic0 = force RTS output to a logic 1 (normal default condition)
logic1= force RTS output to a logic0 MCR[0] DTR
logic0 = force DTR output to a logic 1 (normal default condition)
logic1= force DTR output to a logic0
